Showing papers on "Comparator applications published in 1995"

Current comparator automatic output control

Abstract: A circuit for controlling the output level of a power amplifier is disclosed. A current comparator (230) compares a reference current with a sensed current which is representative of the power amplifier current state. The reference current is used not only for comparison with the sensed current but also for setting the power amplifier (104). The current comparator (230) provides an output, based on the comparison, that is coupled to the power amplifier so that the power amplifier current is maintained at an optimum level for minimizing temperature dependent variations and substantially leveling the power of the power amplifier.

Computer system protection device

Abstract: A protection device for a micro-controller chip comprising a heat sink, a cooling fan, and an overheat alarm The heat sink is adapted to be mounted on a micro-controller chip and is capable of dissipating heat generated by the micro-controller chip The cooling fan disperses the heat dissipated by the heat sink into the surrounding atmosphere The overheat alarm includes a temperature sensor, a voltage comparator, an oscillator, and alarm sound generator The temperature sensor converts a temperature of the heat sink into electrical signals and outputs a voltage proportional to the temperature of the heat sink A voltage comparator compares the voltage output from the temperature sensor with a reference voltage signal and outputs a comparator output voltage The oscillator generates and outputs an oscillating voltage signal The alarm sound generator is enabled by the comparator output voltage from the voltage comparator for generating an alarm sound by operating a speaker in accordance with the input oscillating voltage signal from the oscillator

Address transition detection sensing interface for flash memory having multi-bit cells

Abstract: An address transition detection interface is disclosed for a sensing circuit that determines a state of a memory cell having n possible states, where n is greater than 2, and wherein no decoding logic is required to translate outputs of comparators into binary bits. In the case where n is 4, the sensing circuit includes a first reference corresponding to a first threshold voltage level and a first comparator coupled to the memory cell and to the first reference. The first comparator compares a threshold voltage level of the memory cell to the first reference and provides a first result of the comparison as output. The sensing circuit further includes a second reference corresponding to a second threshold voltage level and a third reference corresponding to a third voltage level. A second comparator has one of its inputs coupled to the memory cell and its second input is selectively coupled to either the second reference or the third reference. A selector circuit selects between the second and third references in response to the first result. The selector circuit couples the second reference to the second comparator if the threshold voltage level of the memory cell is less than the first threshold voltage level. The selector circuit couples the third reference to the second comparator if the threshold voltage level of the memory cell is greater than the first voltage level. A forcing circuit provides the first reference to the second comparator in place of the second and third references for a predetermined period following the output of the first result by the first comparator and prior to the selective coupling to the second comparator by the selector circuit of the second reference or the third reference.

Comparator circuit with hysteresis

Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses a parallel transistor and an enabling transistor connected in parallel to one of the differential pair transistors to create hysteresis. The parallel transistor and enabling transistor are used to generated an effective offset voltage which must be overcome for the comparator to switch states.

Low-voltage CMOS comparator

Abstract: A MOS comparator which includes a capacitor connected in an electrical path between two amplification stages. The comparator also includes a voltage source, and a switch is provided between the voltage source and the input of the second stage. A variability of electrical parameter of the voltage source can be matched with a parameter of the amplification stage. The comparator can also include another switch between another voltage source and a third stage, with the two voltage sources providing different voltages. A comparator gain stage includes circuitry for deriving a differential current from the two voltages. Circuitry is also provided for loading the differential current to derive an amplified difference voltage. Further circuitry is provided for bypassing the loading circuity to reduce a quiescent voltage drop associated with the loading circuitry.

Dual threshold current mode digital PWM controller

Abstract: A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

High-speed bit synchronizer with multi-stage control structure

Abstract: A high-speed bit synchronizer comprising a phase comparator for detecting a phase relationship between a center of an eye pattern of input NRZ data and a rising transition of a clock pulse from a voltage controlled oscillator (VCO) whenever the input NRZ data makes a transition, a frequency comparator for detecting a frequency relationship between a multiple of a period of the clock pulse from the VCO and a multiple of a period of an external reference clock pulse whenever the external reference clock pulse makes a rising or falling transition, phase and frequency comparator gain limiters for limiting gains of the phase and frequency comparators, respectively, a frequency synchronous signal detector for generating frequency synchronous and asynchronous signals in response to an output of the frequency comparator, a phase difference output controller for controlling the transfer of an output of the phase comparator gain limiter in response to an output of the frequency synchronous signal detector, a low pass filter (integrator) for outputting a voltage of a low frequency component to the VCO in response to an output of the phase difference output controller and an output of the frequency comparator gain limiter, and a frequency-divider for frequency-dividing the clock pulse from the VCO at a desired ratio.

Comparator with built-in hysteresis

Abstract: A comparator with a built-in hysteresis is disclosed The comparator has a differential input stage, an output stage, and a bias circuit with a hysteresis circuit The hysteresis circuit selectively applies a bias voltage to the differential input stage to achieve the hysteresis

Circuit for generating a reference voltage and detecting an undervoltage of a supply voltage and corresponding method

Abstract: A circuit for generating a reference voltage and detecting a drop in a supply voltage, comprising at least one threshold comparator having an input terminal and an output terminal, and a voltage divider connected between a first supply voltage reference and a second voltage reference and connected to the input terminal of the comparator, further provides for the output terminal of said comparator to be connected to the input terminal through at least one feedback network comprising at least one current generator. The feedback network further comprises a buffer block having an input terminal connected to said comparator and a first output terminal connected to a switch which is connected between a circuit node of said voltage divider and the second voltage reference.

Phase error processor circuit with a comparator input swapping technique

Abstract: A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs of a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams. The output of the exclusive-OR gate is coupled to the input of a D flip flop which is latched once per window. The output of the D flip flop is an UP/DOWN signal which controls an oscillator, which generates the local clock signal, to advance or retard the phase of the local clock in response to the condition of the UP/DOWN signal.

Monitoring device for 2-wire bus line system

Abstract: The monitoring device includes at least three comparators (120-122) in a receiving circuit of bus subscriber, device to apply two signals line voltages to the inputs of 1st. comparator, one of signal line voltages and auxiliary voltage to the inputs of second comparator and the other signal line voltage to the inputs of the third comparator. The logic circuit (140) is based on injection-injection logic. A logic circuit receives output signals of at least the 2nd. and 3rd. comparators at the same time, to signal a fault-free state of the bus system when the received comparator output signals are in agreement, and to signal a fault state on the bus system when the received comparator output signals are not in agreement. The comparators are arranged as receiving comparators for undisturbed operation and for single-wire operation in the case of different fault states, and the monitoring device comprises demultiplexer operable to select one of comparator outputs for evaluation.

Electric machine controller

Abstract: A controller for a switched electric machine, especially a switched reluctance motor, takes timing information from a rotor position transducer to generate a switch-off output at a point near maximum phase inductance in a phase inductance cycle. A switch-on signal is generated after a delay but still within the phase inductance cycle. A simple form of single-pulse control is thereby achieved. A comparator is also provided which monitors phase winding current. A pulse generator is actuated by the comparator when the winding current exceeds a reference level and is used to control the motor in a chopping mode at low speeds and is disabled by the comparator at higher speeds when the single-pulse control is used.

Oscillators having charge/discharge circuits with adjustment to maintain desired duty cycles

Abstract: An oscillator comprises a comparator and first and second switches for alternately connecting first and second respective reference voltages to a first input of the comparator. A capacitor is connected to a second input of the comparator, and a current source and a current sink are alternately connected to the capacitor via third and fourth switches. The first and third switches are closed simultaneously based on one output level of the comparator, and the second and fourth switches are closed simultaneously based on the other output level of the comparator. This causes the output of the compartor to alternate and thereby generate an oscillation signal. To provide precision in the duty cycles, either the second reference voltage, the current source or the current sink is adjusted to maintain desired duty cycles of the high and low levels output from the comparator. The adjustment to the second reference voltage, current source or current sink is based on an average voltage of the capacitor in relation to a third reference voltage.

CMOS strobed comparator with programmable hysteresis

Abstract: A comparator produces a digital output based upon a differential input signal and hysteresis. To inject positive feedback, a second differential pair is added. This feedback pair is nominally identical to the input pair. If the comparator has recently sensed a positive input of sufficient magnitude to drive the comparator output high, switches are turned on coupling a positive hysteresis voltage to the inputs of the feedback differential pair. By coupling a fixed current differential from the second differential pair to the input differential pair, the effective switching threshold of the comparator is changed. A non-overlapping clock generator is formed so that the switches will not turn on simultaneously so as to short the hysteresis reference voltage source. The hysteresis voltage source can be centered at any voltage that does not exceed the common mode range of the input pair. In a first alternative embodiment, the ratio of feedback is not unity, such that the hysteresis voltage is linearly related to the noise margin. In a second alternative embodiment, a more complicated switch matrix can be used to provide a variety of different hysteresis voltage levels. By including a more complicated switch matrix having several taps, the level of hysteresis can be made programmable. In a third alternative embodiment, the comparator structure according to the present invention is translated so that the differential pairs are formed with p-channel transistors. In a fourth alternative embodiment, the programmable hysteresis is applied to a sense amplifier.

Open collector communications link

Abstract: A bidirectional, long-distance open collector link is constructed between a pair of spaced-apart open collector ports, with each of the ports being coupled to one input of a comparator. The other input of the comparator is responsive to a reference voltage and the comparator of the opposite port via an extended conductor. A first diode poled to pass current from the respective port is coupled between inputs of each comparator, and a second diode is coupled in the extended conductor to pass current to the opposite port. As such, when a first port goes LOW, a first comparator operatively associated with that port provides a LOW to the input of the second comparator, causing it to provide a HIGH output and also pulls the second port LOW. The HIGH from the second comparator is used to clamp the first comparator LOW as long as the port asserts a LOW.

Preamplifier noise filtering circuit

Abstract: A circuit for rapidly charging a capacitor for a transition between operating states is provided. A controlled reference voltage is provided to reference the circuit. A comparator compares signals at the comparator inputs and provides an output dependent upon the comparator input signals. The output of the comparator enables or disables a controlled current charging circuit. The current charging circuit rapidly charges the capacitor when enabled.

Chopper type comparator for an analog-to-digital converter

Abstract: A chopper type comparator is disclosed and implements a differential configuration with inverter amplifiers each having a control terminal. The comparator, therefore, successfully cancels noise of the same phase while preventing a current from constantly flowing therethrough. The cancellation of noise of the same phase, coupled with differential signals, doubles the signal range in the same voltage range, compared to a single end configuration. Hence, a high resolution is achievable even when a power source voltage is low.

Pulse width modulated amplifier

Abstract: A class-D pulse width modulated amplifier. The amplifier includes a current switch, an integrator and a comparator connected in a feedback loop. The feedback loop generates an ultrasonic frequency carrier which is utilized in the pulse width modulation of an audio input signal. In one embodiment a current switch and an audio input source are in electrical communication with an integrator. The output signal of the integrator is the input signal to a phase split differential output comparator having hysteresis. The differential output signals of the comparator are the input signals both to a load and to the current switch, thereby completing the feedback loop. In one embodiment the current switch includes compression circuitry.

An HTS quasi-one junction SQUID-based periodic threshold comparator for a 4-bit superconductive flash A/D converter

Abstract: An all high-T/sub c/ periodic threshold comparator for application in a 4-bit superconductive A/D converter has been realized and tested. The theoretical threshold curve of the comparator is calculated and compared to the measured results. Furthermore, the thermal noise immunity and the influence of flux-flow are considered, resulting in practical design constraints for the comparator circuit. >

Method and apparatus for calculating a divider in a digital phase lock loop

Abstract: A digital phase lock loop (DPLL) (10) includes a first comparator (12), a second comparator (14), a third comparator (16), and adjuster (18), feedback divider (20), a threshold unit (21), a digital oscillator (23), and a loop filter (24). The first comparator (12), loop filter (24), digital oscillator (23), and feedback divider (20) of the DPLL (10) operate to produce a controlled oscillation. The second comparator (14), third comparator (16), and adjuster (18) provide a divisor to the feedback divider (20) that allows the DPLL (10) to operate with a variety of unknown system clock (22) frequencies.

Double-input analog-to-digital converter using a single converter module

Abstract: The disclosure is an analog-to-digital converter of half-flash type providing for the multiplexing of two analog input signals and therefore requiring only one converter module. It includes a coarse comparator block used to determine the most significant bits of the converted signals and also determining the voltage range for two fine comparator blocks that determine the least significant bits of the converted signals, wherein each of the input signals is connected to a fine comparator block and said coarse comparator block compares alternatively the first and second input signals with a reference voltage. The analog-to-digital converter can be advantageously used for processing television signals.

Micropower RC oscillator having hysteresis produced by switching current sources to a transistor

Abstract: An RC oscillator operates at very low current levels and manifests very brief internal component delays. The RC oscillator does not employ a conventional comparator and a conventional hysteresis circuit for changing reference voltages on the comparator. Instead, the RC oscillator includes a plurality of amplifiers. Hysteresis is achieved by changing the threshold voltage of one of the amplifiers. The threshold voltage is changed by switching different current values through the transistor so that the current for activating the amplifier is different from the current for deactivating the amplifier.

Controller for power supply

Abstract: PROBLEM TO BE SOLVED: To provide a controller having a master slave function and capable of making a power supply small and effective in a well-balanced way, by operating different kinds of switching circuits independently by each controller under each adequate condition without generating a switching beat. SOLUTION: A control system is made up of an error amplifier Err2, an output buffer Buf2, and a comparator Comp2 in a slave-side controller CD2-a. A frequency dividing circuit div1 is provided on the output side of the comparator Comp 2. The comparator Comp2 is operated by a triangular wave voltage in accordance with a synchronous signal RSS. Then, the dividing circuit div1 divides a pulse frequency of a pulse output signal Po2 of the comparator Comp2 into a lower frequency of 1/n with compared with pulse output signal from a master-side controller. COPYRIGHT: (C)1997,JPO

Voltage comparator and monitor

Abstract: A device for comparing two DC voltages (U1, U2) comprises a voltage comparator (3) having two inputs (9, 11). One of the two voltages (U1, U2) to be compared to each other is fed directly into one of the inputs (9, 11). The other voltage enters a voltage-conversion device (2) in which the voltage to be compared is superimposed with the DC voltage (8) so that a DC voltage arises at the output (7) of the voltage-conversion device (2), which voltage periodically fluctuates back and forth between an upper and a lower amplitude value in the cycle of the square-wave signal (8). The distance between the two amplitude values corresponds to the tolerance band within which the two voltages (U1, U2) to be compared with one another must be identical. The voltage signal obtained from the voltage-conversion circuit (2) enters the other input (9) of the voltage comparator (3), which then only supplies an AC signal at its output (15) if the upper amplitude value is greater than and the lower amplitude value is smaller than the DC signal fed into the other input (11) of the comparator (3).

A mismatch free CMOS dynamic voltage comparator

Abstract: This paper describes an analog voltage comparator. It uses a current-mode approach for the storage of one input and reuse of the same transistors for both analog inputs, thus avoiding the problem of transistor mismatch encountered in differential structures. The circuit has been fabricated in a digital 0.9 /spl mu/m CMOS process and was tested with a power supply of 1.5 V. The measured offset is 1 mV.

Electronic circuit comprising a comparator

Abstract: This invention relates to the operation of common electronic comparators and particularly to an electronic circuit with a comparator for the operational test of integrated circuits (ICs) According to the invention, the electronic circuit comprises a common comparator (1) with an input (2), an output (4) and a reference input (3) To the reference input (3) a constant reference voltage (V ref ) is applied The input voltage (V in ) to be compared with the reference voltage (V ref ) is superimposed to a time-dependent signal (8) and the resulting voltage is applied to the input (2) of the comparator (1)

Voltage-frequency converter circuit with temperature compensation

Abstract: In a voltage-frequency converter having an integration circuit for integrating an input voltage signal in positive and negative directions, a first comparator is connected to switch integration direction of the integration circuit and a second comparator is connected to compare an integration output signal and a threshold signal. A delay circuit delays one of rising and falling edges of a second comparator output signal to be used as the threshold signal. The second comparator compares the delayed signal with a reference signal varying in accordance with a temperature and produces a second comparator output signal by which the integrating direction is switched. By the use of the delayed signal and the temperature dependent reference signal, a frequency change in the second comparator output signal caused by response time delays of the comparators is compensated for.

Multi-comparison analog-to-digital converters using the interpolation principle

Abstract: The disclosure concerns a so-called "auto-zeroing" comparator of two analog input voltages to be compared, and an analog-to-digital converter using a set of auto-zeroing comparators enabling the number of comparators required for an analog-to-digital conversion to be reduced. The main originality of the invention is that this comparator includes a second stage constituted by an inverter function provided in such a way that only a first transistor is controlled on its gate by the previous stage, a second transistor having its gate and drain short-circuited by a switch during the auto-zeroing phase, and a third transistor used as a capacitor and connected to the gate of said second transistor and also to the supply voltage. The present invention is applicable in particular to all types of CMOS multi-comparison ADCs using at least one "auto-zeroing" comparator.

Supply voltage selection circuit for a voltage controller

Abstract: The automatic output voltage selection circuit operates by connecting the input of the voltage regulator circuit (1) to different incoming voltage levels (Vin1, Vin2), using a controlled switch (2). The operation of the switch is controlled by a circuit (3,4) comparing the input and output voltages over the regulator. The switch control circuit has a group of comparator circuits (C1,C2) with the output voltage (Vout) connected to one input and a supply line connected to the other input. A third comparator (C3) has the supply lines connected to each of its inputs. The outputs of the comparators are delivered to a logic circuit (3) which controls the position of the switch in response to the comparator outputs pattern.

Charge integrating-type analog to digital converter employing rapid charge neutralization and N-bit feedback

Abstract: A Sigma Rho A/D converter (10) includes a transconductance element (R) having an input node for receiving an input voltage signal V in and an output node providing an analog current I in ; a charge integrator (12) having an input coupled to the output node, the charge integrator having feedback provided by an integrating capacitor C and an output node providing an output signal V o ; and a clocked voltage comparator (14) having an input coupled to V o for comparing V o to a reference potential. An output of the comparator updates in response to an occurrence of a first clock signal CLK1. A current sink (16) is switchably coupled to the output node of the transconductance element as a function of the logic state of the output of the comparator. A sum and dump accumulator (18) has an input coupled to the output of the comparator and an output having N output bits, and operates to sum together individual ones of first logic states and outputs a sum value on the N output bits in response to an occurrence of a second clock signal CLK2. The frequency of CLK2 is equal to CLK1/N. A unique bit stream is output from the comparator (14) for each allowed input voltage such that complete information about the input voltage is embedded within, or encoded by, the bit stream output from the comparator.