Showing papers on "Comparator applications published in 1998"

1 GHz 64-bit high-speed comparator using ANT dynamic logic with two-phase clocking

Abstract: A high-speed 64-bit comparator using two-phase clocking dynamic CMOS logic with modified noninverting all-N-transistor block is presented. The pull-up charging and pull-down discharging of a comparator unit are accelerated by inserting two feedback MOS transistors between the evaluation N-block and the output. Detailed simulation results reveal appropriate L/W guidelines for the all-N-transistor block design. To increase throughput a parallel tree structure with two-phase clocks is employed. The comparator units of two adjacent layers are triggered by two out-of-phase clocks so that their individual outputs are pipelined without using extra hardware, e.g. latches. The operating clock frequency is 1.0 GHz while the compared output of two 64-bit binary numbers is done in 3.5 cycles.

Radio receiver and method of operation

Abstract: A gain compensation loop suitable for a quadrature receiver comprises a signal strength comparator having in-phase and quadrature signals fed to respective inputs of the signal strength comparator. The signal strength comparator outputs a signal which represents the difference in strength between the in-phase and quadrature signals. The signal output from the signal strength comparator is input to a gain adjuster which adjusts the gain of the in-phase or quadrature signal in accordance with the signal from the signal strength comparator to bring the in-phase and quadrature signals towards the same strength.

Data clock recovery PLL circuit using a windowed phase comparator

Abstract: A data and clock recovery phase locked loop circuit comprises a data transition detector block to detect transitions of random input data and to produce a window signal. A delay block delays the random input data to produce delayed random input data. A phase comparator block is connected to the delay block and compares phase of the delayed random input data with phase of a feedback signal to produce a phase compared signal. A charge pump block is connected to the phase comparator block and produces output voltage in response to the phase compared signal. A filter block is connected to the charge pump block to filter the output voltage into DC voltage. A voltage controlled oscillator is connected to the filter block to generate the clock signal which has a frequency depending on the DC voltage. A multiplexer block is connected to the voltage controlled oscillator, the data transition detector block, and the phase comparator block and selects one from a predetermined logical level and the clock signal to supply a selected signal to the phase comparator block as the feedback signal.

A 4-D chaotic oscillator based on a differential hysteresis comparator

Abstract: A design approach for higher orders of chaotic systems is proposed. The chaotic oscillator presented is hierarchically modeled and simulated at the system, building-block, and circuit levels. The approach shows that the finite response times of hysteresis elements can be used to increase the order of differential hysteresis comparators. The hysteretic comparator demonstrated is a differential hysteresis which provides two orders of freedom and three possible output values. Experimental results are given for a triple-scroll chaotic oscillator constructed using a RC-opamp design approach. Results from the experimental four-dimensional system are In good agreement to theoretical results.

Method and circuit for calibration of flash analog to digital converters

Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.

Wide common-mode differential receiver with precision input referred offset

Abstract: A differential receiver having a precision input referred offset and a wide CMR, wherein a pair of differential-difference amplifiers are used as differential comparators. The differential-difference amplifiers are configured to allow a precision input-referred offset to be set by the use of two reference voltages. The differential comparators each have a common-mode range over a different portion of the rail-to-rail voltage range. A first one of these differential comparators is activated when the input common-mode voltage is above a threshold level. A second differential comparator is activated when the input common-mode voltage is below the threshold. The output of the differential comparator that is selected is to provide a comparison output signal, thereby achieving a wide CMR. The selection of either the first or second differential comparator is made by a selection circuit that includes a differential Schmitt Trigger and a multiplexer.

Magnetic disk drive read channel with digital thermal asperity detector

Abstract: A thermal asperity-tolerant read channel is provided for a magnetic disk drive. Thermal asperities are detected by a digital detector which includes a pre-filter, a first threshold comparator and, optionally, a second threshold comparator. The pre-filter reduces noise and signal variation in the analog-to-digital converter output to enable better detection of a DC shift caused by a thermal asperity. The first threshold comparator compares the pre-filter output to a predetermined level; if the predetermined level is exceeded, the comparator output is set to one state, providing an initial indication of the presence of a thermal asperity. The optional second threshold comparator determines whether, out of a predetermined number of comparator outputs, the number in the one state exceeds programmd value; if so, the second threshold comparator outputs a final indication of the presence of a thermal asperity. In such a manner, accurate detection of thermal asperities is enhanced while reducing the likelihood of false detection. When a thermal asperity is detected, one or more of the following features can be activated to reduce the adverse effects of the thermal asperity: a squelch connected to the inputs of the variable gain amplifier; a loop-hold feature to maintain channel parameters such as timing, offset and gain until the effects of the thermal asperity have dissipated; and a user data erasure pointer to flag data which has been corrupted by the thermal asperity and which needs to be corrected by ECC circuitry.

Analysis of the behavior of a dynamic latch comparator

Abstract: This brief deals with the behavior of a dynamic latch used as a voltage comparator. A detailed analysis of the fine settling phase is reported, putting in evidence the non-idealities which lead to comparison errors. A technique to minimize such errors is suggested. An experimental chip has been fabricated and measurements are reported and discussed.

Low-power column parallel ADC in CMOS image sensors

Abstract: A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.

Apparatus and method for testing fuses

Abstract: A voltage is applied across a control resistor, and the voltage is caused to decay. The decay is monitored by a testing circuit such as a comparator. When the voltage across the control resistor has decayed to a value less than or equal to a reference voltage in the comparator, a switch time period is established. Fuses in a memory device are tested against the established switch time period. The fuses are tested in a similar fashion: a voltage is applied across the fuse being tested, and the voltage is caused to decay. The comparator monitors the decay of the voltage across the fuse. If the resistance value of a fuse being tested is within specification, the comparator changes its state at a time equal to or less than the switch time period established for the control resistor. Testing time for fuses can further be minimized by having an external access to the reference in the comparator. In establishing the switch time period by applying a voltage across the control resistor, the voltage of the reference in the comparator is adjusted to establish quicker switch time periods against which fuses are tested. In this manner, testing time is minimized.

CMOS comparator output circuit with high gain and hysteresis

Abstract: A comparator circuit (100) produces a binary output voltage at an output (109) in response to a time varying input signal received at an input (108). The comparator circuit includes an output circuit (106) having a first current mirror (202), a second current mirror (204), a bias circuit (206) and a helping current source (208). Bias currents are applied in response to the state of the output voltage at the output to increase the gain and the hysteresis of the output circuit.

Automatic regulation of power delivered by ultrasonic transducer

Abstract: An ultrasonic generator has an output circuit for delivering ultrasonic power to a load through a transducer, the generator having an amplitude control input coupled to the output of a comparator, the inputs of which are coupled to a user interface circuit. The output circuit produces voltage and current signals which are applied to a multiplier in the interface circuit, which produces a power signal applied to an error input of the comparator, the interface circuit also having a signal processor which receives a user-input reference and applies it to a reference input of the comparator. The output of the comparator regulates the power output of the generator to the reference level, and is also coupled to an indicator circuit for providing an visual indication of whether or not the apparatus is in regulation.

Line driver calibration circuit

Abstract: A calibration circuit adjusts a differential output voltage from a line driver circuit when the differential output voltage falls outside a specified tolerance range. The calibration circuit includes a sample and hold circuit which samples the differential output voltage and holds a representative signal. A comparator compares the held signal with a reference voltage signal. When the held signal is greater than the reference voltage signal the comparator outputs a LOW signal and when the held signal is less than the reference voltage signal the comparator outputs a HIGH signal. The comparator output signal is stored in a memory circuit of a control logic. The control logic instructs an up/down counter to increment when the comparator output is LOW and to decrement when the comparator output is HIGH. A calibration current source sinks a unit of calibration current when the comparator output is LOW and sources a unit of calibration current when the comparator output is HIGH. The calibration current is added to an input current to calibrate the differential output voltage towards the specified tolerance range. In a next cycle of the calibration sequence, if a new comparator output signal is different from that stored in the memory circuit, the calibration sequence ceases. However, if the new comparator output signal is the same as that stored in the memory circuit the calibration sequence continues.

Multilevel hysteresis comparator forms for direct torque control schemes

Abstract: Multilevel hysteresis comparators are discussed, including a new quasi-form, which incorporates standard hysteresis with error reference levels, for use in direct torque control schemes for induction motors.

Auto zero circuitry and associated method

Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.

Analog-to-digital converter circuit

Abstract: An analog-to-digital converter circuit, such as a flash-type A/D converter, has a plurality of voltage comparators. Each voltage comparator has first and second input terminals and an output terminal. The voltage comparators are arranged in order of reference voltages V ref1 , V ref2 , V ref3 , V ref4 , and V ref5 supplied to the respective second input terminals of the voltage comparators. Each voltage comparator is connected to the adjacent voltage comparator and the adjacent voltage comparator but one via a first resistor and a second resistor, respectively. The presence of the second resistors makes it possible to improve the degree of contributions of the voltage comparators positioned farther away from the center comparator. Accordingly, conversion deviations are reduced when the outputs of the respective comparators are added and averaged, thereby enhancing conversion precision. As a consequence, the voltage comparators are improved in comparison precision and comparison speed.

Receiving circuit and method for a controlled area network system

Abstract: A receiving circuit is described for a CAN (Controlled Area Network) system with digital data transfer via a bus with parallel, redundant pulse signal transfer via two fines. The receiving circuit includes a comparator circuit assembly for differential evaluation of the two pulse signals received via the two lines, with an offset voltage being superimposed on the pulse signal received via one of the two lines prior to said differential evaluation. The comparator circuit assembly superimposes both a positive offset voltage and a negative offset voltage. A bistable multivibrator circuit is connected between the output side of the comparator circuit assembly and the output of the receiving circuit.

Phase-locked loop circuit with dynamic backup

Abstract: A phase-locked loop circuit with dynamic backup is disclosed. The phase-locked loop circuit with dynamic backup includes a phase comparator, a lowpass filter, a voltage-controlled oscillator, and a detection circuit. The phase comparator compares an input reference signal and a feedback output signal from an output of the phase-locked loop circuit for generating a voltage signal representing the phase difference between the input reference signal and the feedback output signal. After the voltage signal is filtered by the lowpass filter, the filtered voltage signal is sent to the voltage-controlled oscillator for generating the feedback output signal. Coupled to the phase comparator, the detection circuit detects whether or not the phase-locked loop circuit is in lock with the input reference signal. In response to a determination that the phase-locked loop circuit is not in lock with the input reference signal, the detection circuit directs the input reference signal to bypass the phase comparator, the lowpass filter, and the voltage-controlled oscillator.

Buffer circuit for microprocessor output in motor vehicle

Abstract: The circuit is connected between a microprocessor (1) and a control element in a motor vehicle. It contains a comparator (2) circuit whose input (21) is connected to the microprocessor output (11). When a defined voltage level is reached at the input the comparator switches a voltage between a high and a low level which is applied to the control element (3). An energy storage device (C) buffers the input of the comparator circuit.

Self-resetting comparator circuit and method

Abstract: A comparator circuit and method for comparing first and second inputs. First and second input capacitors are provided for storing first and second voltages indicative of the first and second inputs when the circuit is in a sample phase. A comparator stage coupled to the first and second input capacitors switches from a measure state to one of first and second output states when the comparator circuit is in a hold phase based upon the relative magnitudes of the first and second inputs. Reset circuitry operates to discharge the input capacitors when the comparator stage switches to one of the output states. During a subsequent sample phase, the discharged input capacitors can be rapidly charged to new voltages thereby increasing the operating speed of the comparator circuit.

Infinite sample-and-hold circuit

Abstract: An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry. The ADC is preferably of the successive approximation type. The comparator/buffer is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.

Wien-bridge chaotic circuit with comparator

Abstract: A Wien-bridge-based circuit generating chaotic oscillations has been designed and investigated both numerically and experimentally. The oscillator contains an operational amplifier, a Wien-bridge used as a resonance loop, an additional RC inertial circuit, and a comparator employed as a nonlinear device. The waveforms and the Lyapunov exponents are presented. The synchronisation properties have been investigated.

Power controller for a switched reluctance motor with a high frequency noise filter

Abstract: The chopping power controller reduces switching error due to the noise in the current detected signal. The chopping power controller includes a switching member (18a) for supplying power to an electric load (1a) and a current sensor (2) for detecting electric current flowing through the electric load (1a). The detected electric current is compared by a comparator (16a, 30a) to a target value. The output from the comparator is supplied to a filter (23) for outputting identical signal (k) as the comparator (16a, 30a) after the comparator (16a, 30a) keeps the same level signal for a period of time. The switching member (18a) is turned off when the detected electric current continuously exceeds the target value for the period of time set at the filter (23). The filter (23) may removes the noise which has a shorter period than that of the filter (23). In other words, the filter (23) removes high frequency noise from the comparator (16a, 30a) in order to turn off the switching member (18a) accurately. Therefore, less switching error is generated due to high frequency noise.

Offset-compensated peak detector with output buffering

Abstract: A peak detector is provided with a comparator and a storage capacitor coupled to the output of the comparator. An analog input signal is supplied via an input capacitor to the inverting input of the comparator. The non-inverting input of the comparator receives an output signal produced by an output buffer arranged in a feedback loop of the comparator. A level shifter is coupled in the feedback loop to dynamically adjust an input signal supplied to the output buffer in accordance with application requirements. The operation of the peak detector is controlled by non-overlapping clock signals supplied to switches at the input and inner feedback loop of the comparator to cancel offset caused by the comparator and output buffer.

Analog-digital conversion device comprising a differential comparator

Abstract: An analog to digital converter transposes the input signal into two differential signals, which are applied to respective inputs of a differential comparator. The output of the differential comparator is linked to the input of the analog-digital converter by a circuitry loop for restoring a DC component of each of the differential signals at the mid-voltage of the conversion range of the analog-digital converter.

Compensated voltage regulator

Abstract: A compensated voltage regulator of the type used in programming non-volatile memory cells of a memory cell matrix that is divided into sectors. The voltage regulator includes a comparator that is connected to a supply voltage. A first input terminal of the comparator is supplied a reference voltage, and a second input terminal is feedback connected to a program line. The control terminal of an output transistor is connected to an output terminal of the comparator, and a conduction terminal of the output transistor is connected to the memory cells by the program line. An output current is passed through a conduction terminal of the output transistor. Further, a compensation circuit is powered by the supply voltage. An input of the compensation circuit is connected to the output terminal of the comparator and to the output transistor, and an output of the compensation circuit is also connected to the output terminal of the comparator. This causes the duplication of a current that is suitably attenuated with respect to the output current and is useful in modifying the output voltage of the comparator.

Dual-threshold comparator circuit utilizing a single input pin

Abstract: A dual-threshold voltage comparator circuit utilizes a single input pin of an integrated circuit and an external resistor network. Appropriate selection of the resistors comprising the resistor network permits independent setting of the dual thresholds of the comparator.

Modulator for generating a RF signal

Abstract: The transmitter includes a first oscillator (LO), a quadrature modulator (QM), a comparator (PFD), a first filter (LF), a second oscillator (HF-VCO), and at least one frequency divider (FT1, FT2). The output of the first oscillator is connected with the first input of the quadrature modulator. Base-band input signals are provided to the second and third input of the quadrature modulator. The output of the quadrature modulator is connected with the first input of the comparator. The output of the comparator is connected with the input of the first filter, and the output of the first filter is connected with the input of the second oscillator. The second input of the comparator is connected with the output of the second oscillator, which provides the HF transmission signal. The frequency divider is connected between the second oscillator and the comparator and/or between the quadrature modulator and the comparator.

Comparator circuit with low current consumption

Abstract: A comparator circuit with low current consumption for driving a sawtooth generator includes two differential amplifiers connected back to back, which control the bias current of an operational amplifier through a current measuring device and a means for impressing bias current. During normal operation, that is to say outside a switch-over point of the operational amplifier, the means for impressing bias current is supplied by a comparatively small standby current. Near the switch-over point of a sawtooth signal, the bias current of the operational amplifier is increased. Since the bias current source supplies a current pulse only at the switch-over point of the sawtooth signal, but remains switched off for the remainder of the time, the comparator circuit current consumption is minimized.

Voltage monitoring circuit

Abstract: The circuit uses a comparator (10) supplied with a voltage obtained from an ohmic or parallel capacitive voltage divider (R1,R2 ; C1,C2), corresponding to the actual value of the monitored voltage (Vcc), and a reference voltage A second comparator (50) similarly receives the monitored voltage and a reference voltage, with a respective storage capacitor (C3,C5) coupled to the reference input (14,52) of each comparator. Controlled switches (28,29,30,34,54,70) are operated by a signal (S) obtained from the output of the second comparator, or the warning signal at the output of the first comparator, for activating the voltage divider and the reference voltage source when the supply voltage drops below its required value.