Showing papers on "Comparator applications published in 2003"

Current sense amplifier

Abstract: A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal node. The first clamping device is coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal node. The second clamping device is also coupled to the reference voltage. A current mirror is coupled between the first and second input of the voltage comparator and is coupled to an active capacitance balancing circuit. The active capacitance balancing circuit may be combined with the voltage comparator. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal node and the second input signal node.

A high-speed magnitude comparator with small transistor count

Abstract: The comparator is a very basic and useful arithmetic component of digital systems An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters The study proposes a fine cost-performance ratio comparator design Based on modified 1's complement principle and conditional sum adder scheme, the proposed design has small transistor count and short propagation delay Post-layout simulations based on TSMC 06/spl mu/m 1P3M CMOS process has completed It shown a 64-b static CMOS comparator of the proposed architecture only needs 1,556 transistors and 42ns

Voltage-glitch detection device and method for securing integrated circuit device from voltage glitch attack

Abstract: A voltage-glitch detection circuit includes a voltage comparator having two input terminals with different capacitance resistance charge/discharge time. Voltage dividers are coupled to the two input terminals of the voltage comparator respectively, and commonly receive a supply voltage. One of the voltage dividers is supplied to the voltage comparator as a reference voltage of the voltage comparator, and the other is supplied as a glitch detection voltage to the voltage comparator.

Comparator circuit, related method of comparing a vector to comparison boundaries and transmitter employing the same

Abstract: The present invention is directed to a comparator circuit for use with in-phase and quadrature phase signals and a method of comparing a resultant vector of the in-phase and quadrature phase signals. In one embodiment, the comparator circuit includes a non-titled comparison circuit that compares a resultant vector of the in-phase and quadrature phase signals to vertical and horizontal comparison boundary member pairs. The comparator circuit also includes a tilted comparison circuit, coupled to the non-tilted comparison circuit, that compares the resultant vector to comparison boundary member diagonals coupled to the vertical and horizontal comparison boundary member pairs. The comparator circuit may still further include a combiner circuit that provides a comparison signal based on signals from the non-tilted and tilted comparison circuits.

Performance analysis of optimised CMOS comparator

Abstract: A high-speed low-power latched CMOS comparator circuit is presented Demonstrated is a circuit optimisation technique to obtain minimum offset error at 500 MHz sampling speed Also, a mathematical model representing the noise in the device is developed After optimisation, the comparator achieved 10-bit resolution on a 1 V differential input at 500 MHz speed and had a noise figure of 4747 dB at this frequency

Apparatus and method for an active power-on reset current comparator circuit

Abstract: An active power-on reset (POR) current comparator circuit creates a POR signal for resetting logic devices and masking reference startup signals during the initial power supply ramp of an integrated circuit. The comparator circuit provides a logic level signal (i.e., the POR signal) that will actuate when a bias current is above a predetermined level as compared to another current. The predetermined level for the bias current is set by a ratio established between two resistance levels within the active POR current comparator circuit.

Controlled hysteresis comparator with rail-to-rail input

Abstract: Comparator circuits, including rail-to-rail comparator circuits, can implement inverter structures such as current-starved inverters to provide hysteresis to the comparator's output. For example, a current-starved inverter can have its input driven by the comparator output and add current to the currents produced by the comparator's input stage. The inverter current can be derived from bias sources used to bias the input stage of the comparator so that the inverter current can track the input stage bias currents.

Offset calibrating comparator array for 1.2-V, 6bit, 4-Gsample/s flash ADCs using 0.13/spl mu/m generic CMOS technology

Abstract: A 1.2-V calibration comparator array for a flash-type ADC has been developed using 0.13/spl mu/m generic CMOS technology. The developed offset calibration technique corrects the offset mismatch better than 6bit resolution. By employing an offset calibration circuit in the comparator array, the comparator array can operate at low supply voltages. To evaluate the comparator array, a-bit flash-type ADC was fabricated that occupies 0.198 mm /sup 2/. With a 1.2-V power supply, it achieves 4.0 GSample/s and consumes 182 mW.

1-V CMOS comparator for programmable analog rank-order extractor

Abstract: A CMOS rail-to-rail comparator operating at low-voltage supply and obtained by using a conventional fabrication process is proposed. Based on the comparator, an analog rank-order extractor with k winner-take-all capability is presented. An experimental chip was fabricated using 0.5 /spl mu/m CMOS technology. Measured results at 1-V supply voltage show a comparator response time of 4 /spl mu/s for 10-mV precision and that, within 4 /spl mu/s, the extractor successfully identifies a 100-mV differential voltage among inputs to find a rank order of the input set.

Comparator offset calibration for A/D converters

Abstract: An A/D converter includes at least one comparator array (COMP1-COMP7) for flash A/D conversion of an analog signal. Means (CCU, SW1-SW7) pro-vide, for each comparator in the array, a common reference signal to both comparator input terminals. Means (CCU, DAC1-DAC7) force each compara-tor in the array into the same logical output state. Finally, means (CCU, DAC1-DAC7) adjust the comparator trip-point for each comparator by a ramp signal until the logical output state is inverted.

Predictive comparators with adaptive control

Abstract: We describe an architecture that adds a linear predictor and adaptive control to a comparator to greatly reduce its delay. The linear predictor feeds an estimated future signal to the comparator to compensate for the comparator's inherent delay. On a cycle-by-cycle basis, an adaptive controller adjusts the comparator's bias current to null residual errors that remain after the prediction. Emphasis is placed on low power consumption, including the development of a linear predictor with no static power consumption. In an experimental 1.5-/spl mu/m VLSI chip implementation, our scheme enabled a 45-fold improvement in the power-delay product of a simple comparator. Our scheme is ideally suited for comparators used in synchronous rectification. It is also broadly useful in applications where an asynchronous comparator is required, such as sensor interfaces, oscilloscope triggers, some types of analog-to-digital converters, and spiking-neuron circuits. The difference equations that govern our adaptive scheme may be represented by a unimodal discrete map. Therefore, near the limits of the scheme's stable regime of operation, we were able to experimentally confirm that there was a period-doubling route to chaos.

Cross-conduction blocked power selection comparison/control circuitry with NTC (negative temperature coefficient) trip voltage

Abstract: Power selection circuitry that may be employed in redundant power supplies. The power selection circuitry includes a comparator, a symmetric resistor array coupled between the comparator inputs and multiple input voltage sources, a plurality of first switching elements, and control logic/drive circuitry coupled between the comparator output and the first switching elements. The first switching elements connect a selected input voltage source to a load. The comparator compares the voltage levels of the respective voltage sources, and provides a voltage indicating which one of the voltage sources is operational to the control logic/drive circuitry, which applies control signals to the first switching elements to connect the operational voltage source to the load. The symmetric resistor array and a plurality of second switching elements assure that symmetric trip voltages with hysteresis are provided to the comparator. The power selection circuitry may be employed in a redundant power supply to block the cross-conduction of current between the multiple input voltage sources, to reduce current spikes during power selection switching, and to satisfy NTC trip voltage requirements of the switching elements connecting the input voltage sources to the load.

Differential comparator systems with enhanced dynamic range

Abstract: Comparator systems are provided that substantially enhance comparator dynamic range. The enhancement is primarily realized by arranging the systems to apply comparator input signals at feedback taps positioned between the upper and lower ends of comparator strings of impedance elements.

Self-calibratable oscillating device and method and ASIC thereof

Abstract: The present self-calibratable oscillating device includes a phase comparator, a clock pad electrically connected to a first input port of the phase comparator, a crystal oscillator electrically connected to a second input port of the phase comparator, an analog/digital converter electrically connected to an output port of the phase comparator, and a memory electrically connected to an output port of the analog/digital converter. The crystal oscillator can be a temperature-compensated crystal oscillator or a surface acoustic wave crystal oscillator. The present self-calibratable oscillating device can further includes a first switch positioned between the first input port of the phase comparator and the clock pad, a second switch positioned between the crystal oscillator and the clock pad wherein the stream direction of the first switch is in reverse of that of the second switch, and a logic control device for controlling the first switch and the second switch.

Comparator with high-voltage inputs in an extended CMOS process for higher voltage levels

Abstract: A circuit and method are given, to realize a high voltage comparator, which generates an output signal for follow-up processing in the low-voltage domain. The high-voltage comparison task is essentially replaced by a current comparison, implemented as a combination of a voltage to current transforming stage with a CMOS current comparator circuit, where only very few parts are working in the high voltage domain. Using the intrinsic advantages of that solution the circuit of the invention is manufactured with standard CMOS technology and only four discrete or integrated extended drain MOS components at low cost. This solution reduces the complexity of the circuit and in consequence also power consumption and manufacturing cost.

A 1-V MOSFET-only fully-differential dynamic comparator for use in low-voltage pipelined A/D converters

Abstract: Low-voltage low-power comparators implemented in standard digital processes are of increasing importance in different integrated applications. In this paper a 1-V fully-differential low-power MOSFET-only comparator with rail-to-rail input swing is presented which can be suitably used in very low-voltage low-power pipelined A/D converters. This comparator utilizes a resistive divider configuration with a MOSFET-only clock booster to supply a higher voltage for the dynamic latch in the intervals that a comparison is to be made. HSPICE simulations of the proposed comparator in a 0.25-mm CMOS process, confirm the rail-to-rail input range of the fully-differential comparator with a supply voltage of 1 V with a decision time of less than 1 ns while driving a capacitive load of 0.2pF. The worst-case dynamic power consumption of the proposed comparator is less than 100mW with a clock frequency of 50MHz.

Servo loop for well bias voltage source

Abstract: A servo loop for a charge pump including comparator. A variable resistor and comparator are in series and couple the output of the charge pump to an enable input. A current source/sink coupled to the variable resistor provide a first input voltage to the comparator, with the second input of the comparator being coupled to ground or Vdd. A shunt circuit in parallel with the load at the output of the charge pump is also coupled to the output of the comparator. The charge pump and shunt are alternately enabled and disabled by the comparator to maintain a body-bias supply voltage. The servo loop may be configured to provide body-bias for NFETs or PFETs.

Driving circuit for driving capacitive element with reduced power loss in output stage

Abstract: A first comparator circuit compares an input voltage from a D/A converter with an output voltage. A second comparator compares the input voltage with a predetermined reference voltage. The second comparator circuit includes an even number of stages of inverters, which are connected together, and analog switches. In the second comparator circuit, the input voltage is quickly input just before the initialization, and then a first analog switch is opened and a second switch is closed, thereby suppressing the power consumption. A switch control circuit controls switching of switches, i.e., from a third switch to a tenth switch, in accordance with the determination output of the second comparator circuit, a write signal, and an output initialization signal.

Comparator with hysteresis

Abstract: The invention relates to a comparator with hysteresis. With existing comparators having internal positive feedback there is the problem of fast switching requiring a high current consumption. The invention provides a comparator with hysteresis which achieves fast switching despite a low current consumption. The comparator comprises a first transistor (M1) and a second transistor (M2) whose gates form the inputs of the comparator. The main current paths of both transistors are connected to each other at one end, with a third transistor (M3) and a fourth transistor (M4) being provided. The gate of the third transistor is connected to the gate of the first transistor and its main current path is circuited between the one end of the main current paths of the first and second transistor and is connected via the main current path of the fourth transistor to the other end of the main current path of the second transistor. The gate of the fourth transistor is connected to the output signal or inverted output signal of the comparator. The comparator in accordance with the invention may be put to use e.g. in an ASK demodulator such as e.g. in transponders.

An unshunted comparator as a device for quantum measurements

Abstract: The unshunted single-flux-quantum SFQ comparator is described for the first time. Its dynamic behavior is surprisingly similar to the familiar resistively-shunted SFQ comparator. For certain parameter ranges both junctions of the comparator may pulse at the same time to create a reflected anti-pulse. This phenomenon is utilized in a new SFQ comparator design with better coherence properties for qubit readout. Considerations of quantum noise for the unshunted SFQ comparator are discussed.

Oscillator with temperature control

Abstract: An oscillator circuit includes a capacitor device, a current source for supplying a current to the capacitor device, a reference voltage, and a control circuit. The reference voltage is a first input to a comparator. An output of the capacitor device and an output of the current source are a second input to the comparator. The control circuit resets the oscillator circuit when the first and second inputs to the comparator are equal.

High speed comparator with blocking switches for SAR convertor

Abstract: Open loop common mode driver for switched capacitor input to SAR. A method for controlling the operation of a SAR conversion cycle. The method includes the steps of first initiating the SAR conversion cycle by connecting one side of a plurality of capacitors in a capacitor array to a first capacitor reference voltage and the other side of the plurality of capacitors to the input of a comparator. This is followed by the step of sequentially switching in a plurality of compare cycles the one side of a select one or ones of the capacitors to a second capacitor reference voltage to change the voltage on the input of the comparator. Then, a compare operation is initiated after initiation of each compare cycle to compare the value on the input of the comparator with a compare reference voltage after a predetermined settling time has elapsed from the beginning of the initiation of each compare cycle. During the compare cycle, transients due to voltage variations on the input of the comparator are reduced as a result of the step of sequentially switching, the reduction operating for a predetermined portion of the associated compare cycle.

Dynamic duty cycle clamping for switching converters

Abstract: A method and system for dynamic limiting of the pulse width or duty cycle of a switched DC-to-DC power supply. The system includes a first comparator coupled to the voltage to be regulated and to a reference voltage for generating an error signal. The error signal controls the duty cycle or pulse width of a PWM. A limiter circuit includes a further comparator which compares the error signal to a second reference voltage to generate a further limiting feedback signal for application to the first comparator. When the error signal tends to rise above a value established by the second reference voltage, the limiter applies a signal to the first comparator tending to reduce the error signal to thereby prevent the error signal from rising sufficiently to produce the undesired operating condition.

Double data rate (ddr) data strobe receiver

Abstract: A data strobe receiver that includes a first comparator. The first comparator has a first input that is coupled to a first reference voltage. The first comparator has a second input that is coupled to a data strobe. The first comparator also has an output. The data strobe receiver also includes a delay element. The delay element has an input that is coupled to the output of the first comparator. The delay element also has an enable input and an output. The data strobe receiver also includes a second comparator. The second comparator has a first input that is coupled to a second voltage reference. The second comparator has a second input that is coupled to the data strobe. The second comparator also has an output. The data strobe receiver also includes a divide-by-X-counter, where X is an integer greater than 1 and less than 129. The divide-by-X-counter has an input that is coupled to the output of the second comparator.

Low power transponder circuit

Abstract: A low power transponder circuit comprises two comparator (62, 104 ; 64, 106) coupled to a signal input section, wherein only a first comparator (62, 104) is active before a valid wake-up signal is detected and validated. The first comparator (62,104) consumes less power than the second comparator (64, 106), and the second comparator (64, 106) operates at a higher speed than the first comparator (62, 104), such that valid received signal processing is performed on a signal from the second, higher speed comparator (64, 106). Reference voltage levels for the two comparators can also be modified during circuit operation with either information stored in the transponder or by data received in a valid received signal.

Method for accurate output voltage testing

Abstract: A method for accurate testing of the output voltage of an integrated circuit comprises enabling a differential voltage comparator on the integrated circuit to be tested. One input to the differential comparator is set to a reference voltage, and the other input is coupled to a node to be tested. A current load is injected at the node, and the output of the voltage comparator can be used to determine if the integrated circuit performs within the specifications set by a manufacturer.

Simplified comparator with digitally controllable hysteresis and bandwidth

Abstract: An apparatus and method of a programmable hysteresis comparator capable of producing a digital signal in response to differential input signals is disclosed. In one embodiment, the programmable hysteresis comparator includes a hysteresis offset programmable circuit that is operable to selectively provide a hysteresis offset in response to a programmable hysteresis offset control signal. The programmable hysteresis comparator further includes a comparator circuit, which is capable of receiving differential input signals. The hysteresis comparator is operable to output a digital signal in response to differential input signals and the hysteresis offset.

A power amplifier system

Abstract: A power amplifier system (1) comprises a control circuit; a power amplifier (3) and a delay device (8). The control circuit comprises a detector (4) for detecting an instantaneous power level of an input signal; a threshold comparator (5); and a power supply voltage source (6). The threshold comparator is provided with a plurality of preset thresholds (TH1, TH2, TH3); wherein the threshold comparator compares the detected power level with the preset thresholds; wherein the power supply voltage (V1, V2, V3 and V4) is switched according to the output of the threshold comparator; and wherein the delay device (8) delays the input signal to the power amplifier to enable the power supply voltage to be adapted to the detected power level, such that the efficiency of the power amplifier (3) is optimised.

Two comparator voltage mode PWM

Abstract: Two comparators are arranged to generate a pulse-width modulator (PWM) control pulse. The first comparator is arranged to start the PWM control pulse, while the second comparator is arranged to stop the PWM control pulse. The first comparator can be a high speed CMOS comparator that includes a built-in offset. The first and second comparators can be arranged such that the built-in offset of the first comparator dominates the overall operation at the start of the control pulse. The start of the PWM control pulse is initiated by a ramp voltage and a predetermined reference level instead of a clock edge. The PWM control pulse can be linearly varied down to a zero pulse width. The PWM control pulse may be used to control the on-time of the switching element in a switching-type converter.

Method and apparatus for detecting interruption of an input signal with cancellation of offset level

Abstract: An input branch of a loss-of-signal (LOS) detector is coupled to a first input of a comparator. A threshold branch of the LOS detector is coupled to a second input of the comparator. An operational amplifier is connected between the input branch and the threshold branch to couple an offset level from the input branch to the threshold branch. The offset level is then cancelled at the comparator.