Showing papers on "Comparator applications published in 2010"

Clocked comparator for high-speed applications in 65nm technology

Abstract: This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement and simulation results show that the proposed design has an average of 31% higher speed and ∼17% less active area than the conventional design.

A CMOS low-power low-offset and high-speed fully dynamic latched comparator

Abstract: This paper presents a novel dynamic latched comparator that demonstrates lower offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage is improved. The complementary version of the regenerative latch stage, which provides larger output drive current than the conventional one at a limited area, is implemented. The proposed circuit is designed using 90nm CMOS technology and 1V power supply voltage, and it demonstrates up to 19% less offset voltage and 62% less sensitivity of the delay to the input voltage difference (17ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.

A/D converter, solid-state image sensing device, and camera system

Abstract: An A/D converter includes: a first comparator that compares an input signal, with a first reference signal which is a ramp wave having a predetermined polarity, and that when the input signal matches the first reference signal, reverses an output signal thereof; a second comparator that compares the input signal, with a second reference signal which is a ramp wave having a different polarity from the first reference signal, and that when the input signal matches the second reference signal, reverses an output signal thereof; and a counter capable of counting up so as to measure the comparison times taken by the first comparator and second comparator, wherein when either of the output signal of the first comparator and the output signal of the second comparator is first reversed, the counter ceases a counting action.

A low-offset high-speed double-tail dual-rail dynamic latched comparator

Abstract: This paper presents a new dynamic latched comparator which shows lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage was improved and the complementary version of the output-latch stage, which has bigger output drive current capability at the same area, was implemented. As a result, the circuit shows up to 25% less input-referred latch offset voltage and 44% less sensitivity of the delay versus the input voltage difference (delay/log(ΔVin)), which is about 17.2ps/decade, than the conventional double-tail latched comparator at approximately the same area and power consumption.

A new low-power high-speed single-clock-cycle binary comparator

Abstract: This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is based on a novel parallel-prefix algorithm which drastically reduces the switching activity of the internal nodes of the circuit. When implemented by using the ST 90nm-1V technology, the proposed 64-bit comparator exhibits an energy dissipation of only 0.77μW/MHz and a delay of 258ps. With respect to a recently published low-power high-speed parallel-prefix adder, the proposed design shows an energy dissipation reduction of 23% and a speed improvement of 7%.

Low dropout regulator circuit without external capacitors rapidly responding to load change

Abstract: A low dropout regulator (LDO) circuit without external capacitors rapidly responding to load change includes a slow pathway and a fast pathway for controlling voltage, wherein the slow pathway for providing precise output voltage includes an operational amplifier I 0 , a driving transistor MPR, a resistor RF 1 and a resistor RF 2 forming an operational amplifier loop, and the fast pathway for responding to rapid load change includes a comparator I 1 , a comparator I 2 , a field effect transistor MN 1 , a field effect transistor MN 2 , a driving transistor MPR, a resistor RF 1 and a resistor RF 2 forming a comparator loop. The circuit is capable of controlling the output voltage by the slow operational amplifier loop and fast comparator loop, so that the load response speed of the LDO is greatly improved without the increase of the system power consumption and external big capacitors.

Buck Converter with Internal Ripple Compensation

Abstract: A buck converter with internal ripple compensation includes a comparator for generating a comparison result, a constant-on-time trigger coupled to the comparator for generating a trigger control signal according to the comparison result, a pre-driver coupled to the constant-on-time trigger for controlling a high side switch and a low side switch, an output module coupled to a first node and a signal output end, and a ripple compensation circuit coupled to the high side switch, the low side switch, the first node, and the comparator for generating a compensation signal outputted to the comparator.

Electronic device and method for DC-DC conversion with variable bias current

Abstract: The invention relates to an electronic device and a method for DC-DC conversion using a comparator for generating an output signal for driving a power switch of a switch mode DC-DC converter. The electronic device is configured to reduce a bias current of the comparator with a first slope in response to a decreasing load and to increase the bias current of the comparator with a second slope in response to an increasing load, wherein the second slope is steeper than the first slope.

A new offset cancelled latch comparator for high-speed, low-power ADCs

Abstract: A new high speed, low power and high resolution comparator architecture is presented. Offset voltage cancellation on latch stage and eliminating the preamplifier stages before regeneration latch in conventional architectures is the key idea proposed in this paper. Equivalent input referred offset voltage is dramatically reduced by controlled negative feedback loop and negative resistance of regeneration latch. The Monte-Carlo simulation results for the designed comparator in 0.18µm CMOS process show that equivalent input referred offset voltage is 0.2mV at 1 sigma while it was 26mV at 1 sigma before offset cancellation. The comparator operates in 500MHz clock frequency while dissipates 600µW from a 1.8V supply.

Current mode digital control of the output voltage of a switching power supply

Abstract: A method of controlling an output voltage of a pulse width modulation (PWM) converter with a PWM signal driving a power switch of the converter may include using a comparator to compare a reference voltage with a scaled output voltage of the converter, incrementing or decrementing an up/down counter at each pulse of a clock signal applied to the counter depending on a state of the comparator, and controlling the comparator to generate the PWM signal with a control voltage selected from a look-up table using a value of the counter.

Dimmer conduction angle detection circuit and system incorporating the same

Abstract: A conduction angle detection circuit, and systems and methods incorporating the same, is disclosed. The circuit includes a comparator having a first input and a second input, and configured to provide a pulse-width modulated output in response to comparison of signals at the first input with signals at the second input. The output has a pulse width representative of a dimmer setting of a dimmer circuit. The circuit also includes a limiting circuit coupled to the comparator and configured to receive a rectified voltage and to provide a voltage-limited output in response to the rectified voltage to the first input of the comparator. The circuit also includes a threshold supply circuit configured to provide a threshold voltage to the second input of the comparator, and a filter coupled to the comparator. The filter is configured to convert the pulse-width modulated output of the comparator to the dimmer reference level signal.

A low propagation delay dispersion comparator for a level-crossing AD converter

Abstract: This paper presents the design of a continuous time voltage comparator with low propagation delay dispersion. The comparator is intended to be used as a building block for a level-crossing AD converter: a type of AD converter where the sampling moments are triggered when an input signal crosses predetermined threshold levels. This type of system sets very high demands on the time measurement and the comparator to achieve the desired performance. The comparator design is based on several techniques to minimize the comparator propagation delay dispersion. The comparator has been implemented in a 0.35 μm BiCMOS process. Measured results show good agreement with simulations. The slew rate related propagation delay dispersion is measured to 90 ps for an input frequency range from 3 to 10 MHz and amplitudes from 200 mV to 1.65 V. The comparator static power consumption is 9 mW.

4-bit Flash Analog to Digital Converter design using CMOS-LTE Comparator

Abstract: This paper proposes 4-bit, 1.8V Flash Analog to Digital Converter (ADC) design using CMOS-LTE (CMOS Linear Tunable Transcoductance Element) Comparator with 500nm technology. Reference voltages are generated by systematically sizing the transistors of the comparators, thus completely eliminating the resistive ladder network required for the architecture. The PSRR (Power Supply Rejection Ratio) results obtained are compared with 4-bit TIQ (Threshold Inverter Quantizer) Comparator Flash Analog to Digital Converter designed with 500nm technology. It is observed that, with the use of CMOS-LTE Comparator PSRR is improved. The DC simulation results of CMOS-LTE Comparator ADC shows DNL and INL of +0.16/−0.16 LSB and +0.16/−0.104 LSB. The total power dissipation observed is 0.28753 mW.

Sense amplifier for low voltage high speed sensing

Abstract: A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of the comparator is coupled to the low impedance circuit and a reference voltage node. A second input of the comparator is coupled to a data voltage node. The first load circuit loads a reference cell coupled to the reference voltage node. The second load circuit loads a data cell coupled to the data voltage node.

High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator

Abstract: In order to diminish circuit complexity and power dissipation, the simple configuration of the dynamic latch comparator is revisited. This paper proposes and analyzes a comparator that consists of a preamplifier using negative resistance as a load and a double regenerative dynamic latch. A discussion of the dynamic latch is presented and the effect of transistor sizes in the time constant and the offset voltage is explained briefly. The comparator is designed in a 0.6µm CMOS technology. Monte Carlo simulation using Virtuoso® Spectre shows that the comparator has a resolution of 1.8mV and dissipates 750µW of power when working at 40MHz.

Hysteretic power converter with calibration circuit

Abstract: A hysteretic power converter includes a comparator, a calibration circuit, and an output node having an output voltage. The calibration circuit is configured to supply a calibrated voltage to the comparator. The comparator controls the output voltage based on the calibrated voltage and a feedback voltage representing at least a portion of the output voltage.

Adjustable voltage regulator for providing a regulated output voltage

Abstract: Voltage regulators, memories, and methods for providing a regulated output voltage are disclosed. For example, one such voltage regulator includes a comparator circuit, a driver circuit, an impedance circuit, and a modulation circuit. The comparator circuit generates an output voltage according to a difference between a reference voltage and a feedback voltage. The driver circuit is coupled to an output of the comparator circuit and drives the regulated output voltage at an output node according to the output voltage from the comparator circuit. The impedance circuit is coupled to the comparator circuit and provides the feedback voltage to the comparator circuit in response to a detection current from the output node. The modulation circuit is coupled to the impedance circuit and adjusts a modulation current component of the detection current to adjust the regulated output voltage.

Low voltage comparator for high speed ADC

Abstract: This paper presents a design of a high-speed, low-voltage, low power consumption comparator with S-R latch for High speed ADC. The comparator is the most important part in the Flash ADC, since the speed and the resolution is determined by the comparator. In this paper, we do the analysis of the traditional comparator and propose a better structure combing sense amplifier and symmetric S-R latch, which can run faster and provide more stable output signal than the traditional structure. The comparator is composed of a latch based amplifier and a S-R latch which provides stable output. There are many issues in the design of the comparator, we will discuss those design issues in this paper.

Dynamic comparator based comparison system

Abstract: A comparison system including a dynamic comparator, a background offset calibration circuit, and an asynchronous reset timing control circuit is presented. The background offset calibration circuit is coupled to the dynamic comparator, and generates calibration signals in response to reference switching control signals. Where calibration signals are used to calibrate the input refer offset of the dynamic comparator. The asynchronous reset timing control circuit is coupled to the dynamic comparator and the background offset calibration circuit, and generates a control clock signal and the reference switching control signals in response to the output signals of the dynamic comparator and a plurality of basic clock signals. During each clock cycle of the first basic clock signal, the control clock signal is used to control the dynamic comparator to perform two data comparison, one for the input refer offset and the other for a differential input signal.

High-speed low-power Single-Stage latched-comparator with improved gain and kickback noise rejection

Abstract: This paper presents a high speed Single-Stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding Read-Out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and Read-Out circuit is about 300µm2.

Systems and methods for minimizing power consumption

Abstract: A system for reducing power consumption in a transistor-based system includes a measurement circuit and a comparator. The measurement circuit measures a delay of a transistor-based device and produces a control signal corresponding to the measured delay. The comparator compares the control signal to a predetermined threshold. Adjusting a power supply voltage of the transistor-based system based at least in part on a result of the comparison reduces the power consumed by the system.

Squelch Detection Circuit and Method

Abstract: A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.

Discrete time operational transconductance amplifier for switched capacitor circuits

Abstract: A discrete-time operational transconductance amplifier (OTA) with large gain and large output signal swing is described. In an exemplary design, the discrete-time OTA includes a clocked comparator and an output circuit. The clocked comparator receives an input voltage and provides a digital comparator output. The output circuit receives the digital comparator output and provides current pulses. The output circuit detects for changes in the sign of the input voltage based on the digital comparator output and reduces the amplitude of the current pulses when a change in the sign of the input voltage is detected. The output circuit also generates the current pulses to have a polarity that is opposite of the polarity of the input voltage. The discrete-time OTA may be used for switched-capacitor circuits and other applications.

Dual-comparator restricted earth fault protection

Abstract: An intelligent electronic device may provide restricted earth fault protection to components of an electrical power delivery system using both an amplitude comparator and a phase angle comparator configured to independently detect faults. The IED may include selection logic configured to select the output of one of the phase angle comparator and the amplitude comparator, to the exclusion of the other, based on system conditions. Accordingly, when system conditions are such that a phase angle comparator is better suited to detect a fault, selection logic may select the output of the phase angle comparator. Similarly, when system conditions are such that an amplitude comparator may better detect a fault, selection logic may select the output of the amplitude comparator. A protection system may further include an in-zone fault detector configured to detect in-zone faults.

On the design of quaternary comparators

Abstract: Quaternary logic requires a dedicated comparator circuit besides the usual add/sub unit which may not be optimal due to several reasons. In this paper, we have thoroughly discussed various alternative expressions for equality operator which serves as the basis for quaternary comparator. Then we have derived the necessary equations for single qudit comparator and extended it to serial multi qudit comparator. We have also shown the equations and design of single stage parallel comparator where restriction of fan-in is sacrificed for constant speed. We have ended our discussion with the design of a logarithmic stage parallel comparator which can compute the comparator output within log 2 (n) time delay for n qudits.

Low input impedance current comparator using in pulse-width modulation

Abstract: This work presents a design of continuous-time current comparator with ultra low input impedance, which especially benefits on enhancing the accuracy of pulse-width-modulation (PWM). The proposed design reduces the input impedance by utilizing common-gate structure as input stage. The further use of a common-source feedback structure also enables extremely reduction of the input impedance. In addition, the proposed design can be applied to perform precise comparison between two terminals with varied currents since the input impedances are well designed to be balanced. The experiment results demonstrate competitive performance. With input current of 25MHz square wave, the input impedance and propagation delay of comparator are merely 66.9Ω and 2.06ns respectively while the average power consumption is about 1.16mW under the implementation of TSMC 0.35µm CMOS process with 3V power supply.

Microcomputer, Hysteresis comparator circuit, and voltage monitoring apparatus

Abstract: A microcomputer includes a first comparator which compares a voltage to be monitored, with a first reference voltage, a second comparator which compares the voltage to be compared, with a second reference voltage, and an interrupt control circuit which monitors the voltage to be monitored by the first and second comparators in parallel and, when a preset condition is satisfied, generates an interrupt signal.

Hysteresis comparator circuit and semiconductor device incorporating same

Abstract: A hysteresis comparator circuit that compares first and second input signals to output a hysteresis output signal includes a constant current source, a first comparator, a second comparator, and an output circuit. The constant current source includes a load resistor to generate a given constant current. The first comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a first comparison result. The second comparator is controlled by the constant current supplied from the constant current source to compare the first and second input signals to output a second comparison result. The output circuit has a pair of inputs thereof connected to the first and second comparators, respectively, which inverts an output thereof in response to each of the first and second comparison results to generate the hysteresis output signal.

An ultra low-power low-voltage track and latch comparator

Abstract: An ultra low-power comparator which is able to operate at a very low supply voltage is proposed. The low power consumption is achieved by using a new switching scheme that turns off the comparator after the decision is made. The duration of the evaluation time, during which the comparator is on, is automatically adjusted to meet the requirements for different conditions. The proposed comparator is simulated in 0.18μm CMOS technology. The comparator consumes 12.71nW at a supply voltage of 0.5V and clock frequency of 2MHz.

Multiple-input comparator and power converter

Abstract: Techniques pertaining to multiple-input comparator and power converter designs are disclosed. According to one aspect, the present invention discloses a multiple-input comparator comprising a pair of differential transistors connected by a resister. The gate terminals of the transistor pair serve as the input terminals of the comparator for receiving external voltage for comparison. The terminal of the resistor serves as the current input terminal and is either connected to a current source or a current sink. A power inverter utilizing the multiple-input comparator is also disclosed. The power inverter comprises a power switch driven by a PMW signal, a voltage sampling circuit, an error amplifier and a multiple-input PWM comparator.