Showing papers on "Comparator applications published in 2011"

A 1-1-1-1 MASH delta-sigma modulator using dynamic comparator-based OTAs

Abstract: A dynamic comparator-based OTA is introduced as a replacement for a conventional OTA. It performs charge transfer in a switched-capacitor circuit by repeatedly evaluating the polarity of the differential input using a dynamic clocked comparator and injecting current pulses at the output to move the input voltage toward zero. The amplitude of the current pulse is reduced each time the input voltage crosses zero to provide fast but accurate settling of the output voltage. Dynamic comparator-based OTAs are applied to the design of a 1-1-1-1 MASH delta-sigma modulator. The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using zero-crossing-based circuits or comparator-based switched capacitors. Because of the dynamic operation of the OTAs and discrete-time delta-sigma modulator architecture, both bandwidth and power consumption linearly scale with the sampling frequency without any reconfiguration of the modulator.

Realization of All-Optical Digital Comparator Using Single Mode Fabry–Pérot Laser Diodes

Abstract: A two-bit all-optical digital comparator using single mode Fabry-Perot laser diodes (SMFP-LDs) at an input data rate of 10 Gbps is proposed and demonstrated. All-optical comparator is demonstrated using cascaded logic units which are based on injection locking, multi-input injection locking and supporting beam principles for suppressing the dominant mode of SMFP-LDs. Digital comparators are the key components for the decision making circuits, the integral part of the arithmetic and logical units of optical data processors. The output performance of the proposed all-optical comparator is verified with output waveform, rising-falling time, output eye diagram, and bit error rate (BER) at 10 Gbps input Non Return to Zero (NRZ) PRBS of 231-1 signal. The rising/falling time of about 47 ps, clear output waveforms, and clear output eye diagram with an extinction ratio of about 12 dB are obtained. A maximum power penalty of 1.3 dB is measured at a BER of 10-9.

Zero current detecting circuit and related synchronous switching power converter

Abstract: A zero current detecting circuit is disclosed. The zero current detecting circuit includes a first zero current comparator for determining current variation on an inductor of a synchronous switching power converter so as to accordingly turn off a down-bridge transistor of the synchronous power converter; a second zero current comparator for determining whether the first zero current comparator turns off the down-bridge transistor too early or too late and outputting a comparison result, and a counter coupled to the second zero current comparator for ascending or descending a control bit according to the comparison result.

Low power CMOS charge sharing dynamic latch comparator using 0.18μm technology

Abstract: This paper discusses the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed. This topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. This design will be focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves the comparator performance. Simulation results have been obtained using 0.18μm technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and 1.8V input range. Design has been carried out in SILVACO EDA tool, the schematic simulations are using Gateway SILVACO EDA tool and layout simulations are verified using Expert SILVACO EDA tool.

Low-power and low-offset comparator using latch load

Abstract: A low-power and low-offset latched comparator using dynamic offset cancellation and a latch load is proposed. A latch load at the first stage provides the second stage with a large conversion gain and large trigger voltage. It reduces the power consumption and offset voltage of the comparator. The effectiveness of the proposed structure was verified by SPECTRE simulations.

Differential current conveyor based current comparator

Abstract: A New differential current conveyor based current comparator is presented in this paper. Differential current conveyor II (DCCII) is designed, modified, and exploited as a comparator with reduced propagation delay and power consumption. New DCCII decreases propagation delay and increases comparator accuracy considerably. Simulation results using Hspice and 0.18 μm CMOS technology with 1.8V supply voltage confirms a less than 0.63 ns propagation delay at ±1 μA input current. Average power dissipation in ±1 μA input current has a value of 300 μW.

An ultra low-power rail-to-rail comparator for ADC designs

Abstract: This paper presents a novel ultra low-power rail-to-rail comparator which can be suitably used in low-to-medium speed A/D converters. This comparator adopts a preamplifier followed by a dynamic latch structure to achieve fast-decision, high-resolution as well as reduced kick-back noise. A new adaptive power control technique is used to reduce the power consumption of the preamplifier. The circuit is designed and simulated in Global Foundries 65nm CMOS technology. The simulation results have shown that the power consumption of 12-bit comparator is 191.2 nW at the clock frequency of 15 MHz and 0.8 V supply voltage with a delay of 1.17nS.

Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis

Abstract: This paper presents an improved two-stage dynamic comparator using a bulk voltage trimming technique for offset calibration. The comparator requires only a one-phase clock while exerting no extra load on the first stage, leading to higher operating speed. The calibration does not require any extra power supply and does not consume any quiescent current, while increasing the offset calibrating range by a factor of 2 over previous techniques. Detailed analysis of the method of calibrating both stages of the dynamic comparator is provided. Simulation results in a 65nm digital CMOS process show that the comparator is capable of working at a speed of 5GHz with 90uW of power consumption from a 1V power supply, achieving an input-referred offset calibrating range of ±35mV at ∼±2.3mV/step at the typical-typical process corner.

A multi-GHz area-efficient comparator with dynamic offset cancellation

Abstract: In this paper we propose a dynamic impedance modulation technique to significantly improve the speed of comparators utilizing dynamic-offset-cancellation (DOC). Measurements from a 65nm test-chip show that DOC comparators utilizing the proposed technique achieve 6X lower input-referred offset and 9X better power supply noise rejection than a traditional StrongArm comparator with only a 20% speed penalty at identical core comparator area (98µm2) while dissipating 455µW.

High Side Switch Circuit, Interface Circuit and Electronic Device

Abstract: A high side switch circuit includes a switch electrically connected between input and output terminals, a gate control unit, and an over-current sensor unit. The over-current sensor unit includes a resistive element and a comparator. The comparator senses an over-current if a voltage of the resistive element exceeds a threshold voltage. The comparator is adjusted in advance such that the detected voltage at the time of over-current exceeds the threshold voltage. Even if accuracy of resistance value of the resistive element is not high, accuracy of detecting over-current can be improved by adjusting the comparator.

Self-healing analog-to-digital converters with background calibration

Abstract: Calibration of an analog-to-digital converter (ADC) is accomplished via a reference comparator, a first and second multiplexer (MUX), and a finite state machine (FSM). By sampling an analog input with the reference comparator and comparing the results with those of the ADC using the FSM, all the comparators in the ADC can be calibrated without interrupting the ADC's normal operation. The first MUX provides a same reference voltage to the reference comparator as a comparator selected for the calibration, and the second MUX provides the FSM with the output of the selected comparator. The FSM then performs a comparison of the reference comparator and the selected comparator, extracts the polarity of the mismatch, and updates the contents of a memory with the extracted polarity. An offset control in the selected comparator receives a signal corresponding to the extracted polarity stored in the memory and injects offset current into the comparator.

Offset calibration and precision hysteresis for a rail-rail comparator with large dynamic range

Abstract: A rail-rail comparator having an input stage with independent positive and negative differential voltage offset compensation tracks changes in Gm (transconductance) of the input stage. By tracking the changes in Gm (transconductance) of the input stage, hysteresis of the rail-rail comparator becomes insensitive to the input common mode voltage. A two-stage rail-rail comparator may be used for adding hysteresis to a second stage. The first stage of the two-stage rail-rail comparator operates at substantially unity gain. The second stage of the two-stage rail-rail comparator operates as a regular high gain amplifier with hysteresis. Additional circuitry tracks the Gm (transconductance) change of the first stage to make the second stage hysteresis insensitive to the input common mode voltage at the first stage. This also makes it easier to create a programmable hysteresis that is accurate over all input voltage values.

An improved low offset latch comparator for high-speed ADCs

Abstract: This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that equivalent input referred offset voltage is 200 μV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 μW from a 1.8 V supply while operating in 500 MHz clock frequency.

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Abstract: We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 25-bit to 705-bit The ADC is manufactured in a 90 nm CMOS technology, with a core area of 085 mm × 035 mm, a 12 V supply for the core and 18 V for the input switches It has an effective number of bits (ENOB) of 705-bit, and a power dissipation of 85 mW at 60 MS/s

Capacitive physical quantity detector

Abstract: A capacitive physical quantity detector includes: a capacitor having an electrostatic capacitance changeable with physical quantity; a converter converting a capacitance change to a voltage; and a selector having a comparator and a switching element. The converter includes a C-V converting circuit having an operational amplifier for amplifying a first signal from the capacitor, a main switch between input and output terminals of the operational amplifier, feedback capacitors and feedback switches. Each feedback switch connects a feedback capacitor to the main switch when the feedback switch is closed. The selector closes the feedback switches based on a second signal of the converter. The comparator compares the second signal with a threshold voltage. The switching element switches the feedback switches according to a third signal from the comparator to set the second signal smaller than a saturated voltage and larger than the threshold voltage.

Investigation of the relationship between the gray zone and the clock frequency of a Josephson comparator

Abstract: The Josephson comparator is one of the fundamental building blocks of rapid single flux quantum (RSFQ) electronics. Within this circuit family it is the exclusive device which provides logical data processing. The Josephson comparator is also the basic decision element for very fast analog-to-digital converters and sampler circuits for low input power and high-bandwidth signals based on the RSFQ technique. The performance of those devices is fundamentally determined by the characteristics of the Josephson comparator. In this study the gray zone dependency on the clock frequency of a Josephson comparator is investigated by simulations concerning the influence of thermal noise. This investigation is performed for a series of operating points defined by the bias current and different noise levels defined by the operating temperature. In contrast to former investigations, we analyzed the comparator embedded in a realistic environment for output data processing. We identified a characteristic clock frequency fc for a comparator topology designed for a 1 kA cm −2 niobium fabrication technology. The gray zone of 8 μA remains constant for clock frequencies below fc = 15 GHz and starts to increase for larger frequencies. We also found out that this characteristic frequency is independent of the intensity of thermal noise and therefore independent of temperature. (Some figures in this article are in colour only in the electronic version)

Relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation

Abstract: A relaxation oscillator circuit with reduced sensitivity of oscillation frequency to comparator delay variation includes a first current source that generates charging current, a second current source coupled to the first current source to generate reference voltage, a resistor coupled to the second current source to enable generation of the reference voltage, a capacitor coupled to the first current source that is charged based on the charging current, a comparator responsive to voltage corresponding to the capacitor and the reference voltage to generate output voltage, a peak detector coupled to the capacitor to generate peak voltage, an error detector coupled to the peak detector and the second current source to generate an error based on the peak voltage and the reference voltage, and a controller coupled to the error detector to control one of the charging current, offset voltage input to the comparator, and capacitance of the capacitor.

Method and apparatus for input signal offset compensation

Abstract: A method for compensator for comparator offset is provided. A first propagation delay for a first signal traversing a comparator to a first output terminal of the comparator and a second propagation delay for a second signal traversing the comparator to a second output terminal of the comparator are measured. The first and second propagation delays are then compared to generate a comparison result, and the comparator is adjusted to compensate for an input voltage offset based at least in part on the comparison result.

A 500 MS/s 600 µW 300 µm 2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process

Abstract: This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300µm2.

High-speed differential comparator circuitry with accurately adjustable threshold

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.

Electronic circuit, semiconductor device, and electronic device

Abstract: The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset.

Missing code redistribution in pipeline analog to digital converter

Abstract: A stage of pipeline analog to digital converter (ADC) includes a multiplying digital to analog converter (MDAC) and a sub-analog to digital converter (sub-ADC) The sub-ADC includes a comparator and a random offset controller The comparator is coupled to compare a first analog signal received by the stage with a reference signal The random offset controller is coupled to the comparator to apply a random offset to an input of the comparator to randomly distribute errors by the sub-ADC in a digital output of the pipeline ADC

A 20-GHz Bipolar Latched Comparator With Improved Sensitivity Implemented in InP HBT Technology

Abstract: A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic comparator using emitter degeneration resistors is presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs heterojunction bipolar transistor technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low-sensitivity value of 10 mV was obtained.

An analysis on a pseudo-differential dynamic comparator with load capacitance calibration

Abstract: This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived. This analysis enhances understanding of the roles of a transistor's parameters in a pre-amplifier's gain. Based on the calculated gain, a load capacitance calibration method is analyzed. The analysis helps designers' estimation for the accuracy of the calibration and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with the simulation results.

A single-inductor 8-channel output DC-DC boost converter with time-limited one-shot current control and single shared hysteresis comparator

Abstract: This paper describes a time-limited one-shot current control technique used to extend the outputs of a single-inductor multiple-output DC-DC converter without stability and complexity issues The proposed scheme also reliably supports many outputs with unbalanced loads True all-comparator control is realized with a single shared hysteresis comparator and a fixed switching frequency of 800-kHz The maximum efficiency reaches 92% The fabricated 8-channel output chip occupies 24×21 mm2 in a 035-µm CMOS process

Ground fault interrupt circuit for electric vehicle

Abstract: In one implementation, a ground fault interrupt circuit is provided for a utility power connection to an electric vehicle charging unit. The ground fault interrupt circuit may include a gain amplifier having an input connected to be capable of receiving a differential current from a current sensing transformer and a comparator having an input connect to a reference voltage. It includes a rectifier circuit connected between the gain amplifier and the comparator with a charge accumulator circuit coupled between the rectifier and the comparator.

Circuit and method for determining comparator offsets of electronic devices

Abstract: A device includes a comparator, and a selection circuit coupled to the inputs of the comparator. The selection circuit receives reference voltages and a variable voltage. In a normal operation mode, the selection circuit provides the variable voltage and a selected reference voltage to the comparator and the comparator provides an indication based on the variable voltage. In a test mode, the selection circuit provides a first selected reference voltage and a second selected reference voltage to the comparator for determining a switching offset voltage of the comparator.

Sensor interface making use of virtual resistor techniques

Abstract: Some embodiments of the present disclosure relate to a sensor interface module. The sensor interface module includes a comparator having a first comparator input, a second comparator input, and a comparator output. A current- or voltage-control element has a control terminal coupled to the comparator output and also has an output configured to deliver a modulated current or modulated voltage signal to an output of the sensor interface module. A first feedback path couples the output of the current- or voltage-control element to the first comparator input. A summation element has a first summation input, a second summation input, and a summation output, wherein the summation output is coupled to the second comparator input. A supply voltage module provides a supply voltage signal to the first summation input. A second feedback path couples the comparator output to the second summation input.

Energy Efficient Supply Boosted Comparator Design

Abstract: This paper presents a new mixed-signal design technique called supply boosting technique (SBT) and the design of an energy efficient, sub-1 V supply boosted comparator (SBC) in a standard complementary metal oxide semiconductor (CMOS) process. The selected CMOS process does not allow sub-1 V operation with a wide input range due to high threshold voltage (high-VTH) of MOS transistors (+0.8 V/−0.9 V). Despite this, the proposed comparator operates sub-1 V supply voltages with input common mode voltage larger than 60% of supply voltage by utilizing a supply boosting technique. The measured power consumption of the supply boosted comparator for 1 V supply was 90 nW and speed was 6500 conversions per second, resulting in 14 pJ per conversion energy efficiency.