Showing papers on "Comparator applications published in 2013"

Dual loop digital low drop regulator and current sharing control apparatus for distributable voltage regulators

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Metastability detection and correction in analog to digital converter

Abstract: A method of operating an analog to digital converter (ADC) comprises comparing an analog input signal to a reference signal, using a comparator, and generating a comparator output according to the comparison, storing the comparator output in at least one memory unit, monitoring the stored comparator output to determine whether a difference between the analog input signal and the reference signal is within a predetermined range, and detecting a metastability error upon determining that the difference between the analog input signal and the reference signal is within a predetermined range.

A new rail-to-rail ultra low voltage high speed comparator

Abstract: This paper presents a new rail-to-rail input highperformance regenerative comparator suitable for low-voltage low-power applications, e.g. bio-implantable circuits. In this circuit the body of the PMOS transistor is used as comparator's input. A technique is proposed to increase the speed of the circuit. The proposed comparator has a good performance in weak inversion (sub-threshold). Simulations are done in the 0.18-μm CMOS technology with a supply voltage of 0.5 V. The propagation delay time of the second proposed comparator is 16.4 ns, the power dissipation is 20 nW and the power delay product is 0.33 fJ in clock frequency of 5 MHz and input voltage of 500 μV. Also the supply voltage can be decreased to 0.3 V.

Design and Simulation of a High Speed CMOS Comparator

Abstract: Analog-to-Digital conversion process is an electronic process in which an analog signal is changed, without changing its necessary contents, into a digital signal. Latched comparators use positive feedback mechanism (aids in the input signal) to re-generates (amplifies) the analog input signal into a Fullscale digital level output signal [2].This paper presents a CMOS comparator that reduces the overall propagation delay and hence provides higher speed. The design is simulated in 0.25μm CMOS Technology using Tanner EDA Tools. CMOS Comparator shows that the overall propagation delay of the comparator, TPD, is 1.7872e-9 seconds, with a 1.0 V supply voltage.

Led current control

Abstract: An LED control circuit for controlling a current supplied to an LED unit is disclosed. A sense resistor is included for sensing an output current provided from an output node. A comparator circuit is provided for detecting upper and lower thresholds in the output current based on the voltages at ends of the sense resistor, and for controlling a current supply to maintain the current between the thresholds. The comparator circuit comprises a reference current source and reference resistors, for generating upper and lower threshold references. The comparator circuit further comprises a comparator for detecting a mid-range voltage dependent on the output current and deriving a control signal which indicates if the detected voltage is above or below the mid-range voltage. The control signal is used to adjust the reference current source, thereby to vary the upper and lower threshold references to maintain a constant median or average output current.

A high-speed latched comparator with low offset voltage and low dissipation

Abstract: An ultra high-speed latched comparator using a controlled amount of positive feedback cell has been designed in TSMC 0.18 μm CMOS technique. Transmission gate (TG) switches are used to implement the preamplifier circuit. The use of TG switches results in a reduction in the power consumption of the high-speed comparator as well as clock feedthrough and the effect of charge injection. The simulation results demonstrate that it can work at 1.25 GHz suitable for high speed applications, and consumes 273.6 μW with a power supply of 1.8 V at 100 MHz and Monte Carlo simulation shows that the comparator has a low offset voltage approximately 0.499 mV.

High resolution capacitance to code converter

Abstract: An integration circuit including a first capacitor is operatively coupled to a comparator. The comparator is configured to compare a first capacitor voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison. A current generator is operatively coupled with the integration circuit and configured to balance charge on the first capacitor. A control unit is operatively coupled to the comparator and the current generator and configured to balance charge on the first capacitor by sensing the first comparator output and controlling the current generator based on the first comparator output.

Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET

Abstract: A novel latch-based comparator is proposed for Successive Approximation (SA) Analog to Digital Convertor(ADC) with sub-32nm Double Gate MOSFETs(DG-MOSFET). The regeneration time of the latch is improved by using an extra positive feedback which uses the threshold voltage modulation property of DG-MOSFET. Simulation of the proposed comparator with CEA-LETI's DG-MOSFETmodels resulted in a delay of 25ps. The average power dissipation over one clock period is ≤ 1μW up to the clock frequency of 100MHz, which increases as frequency is increased resulting in an average power of 6.54μW at 1GHz, for an input voltage differential of 50mV.

Flash ADC Comparators and Techniques for Their Evaluation

Abstract: We have designed three flavors of a periodic comparator to minimize its phase-dependent nonlinearities. One flavor uses a differential “quasi-one-junction” SQUID (DQOS) quantizer with a low-inductance clocking scheme. The second flavor uses a differential SQUID wheel quantizer, and the third flavor uses a symmetric differential SQUID wheel quantizer with time-interleaved clocks. We also describe a different common mode biasing scheme that gates the quantized signal to apply full signal during the clock aperture, and an attenuated signal outside the clock aperture. We also developed a new performance analysis scheme based on sweeping the dc offset of a single periodic comparator during beat frequency test while following the position of its threshold, which yield both signal reconstruction and duty cycle of the comparator. Using this, we discovered the dependence of the sensitivity of the comparator duty cycle to its dc bias and the slew rate of the signal. This shows a reduction in the effective current amplitude seen by the sampler at increasing slew rates while the quantizer current does not change, indicating a potential performance reduction mechanism arising from finite regeneration time of a clocked comparator that prohibits it from conclusively resolving the polarity of a rapidly oscillating input signal. We also report experimental measurement results for the three flavors of the comparator. Both DQOS and differential SQUID wheel comparators exhibited 4 bits of Gray (3 bits of binary) code resolution for a 20-GHz beat frequency test; 1-bit more than previously demonstrated performance. For a 15 GHz beat frequency, each symmetric differential SQUID wheel time-interleaved comparator exhibited 4.3 bits of resolution. We also demonstrate threshold interleaving of two DQOS comparators to get 4.5 effective bits for a 20-GHz beat frequency test.

Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

Abstract: In this paper, the conventional single-stage latched comparator is improved for both high speed and low noise flash ADCs. In the proposed method for high-speed applications, the common mode level of output voltage is preserved unchanged during both amplification and latch operations, to speed up the comparison of small voltage differences. Also, the amplitude of digital control signals is reduced in the modified low noise comparator by using a fully differential structure to remove the concern of digital noise coupling on analog section. Worst-Case simulation results for all corners, using the BSIM3 model of a 0.35μm CMOS process, confirm that a 5mv differential input can be simply detected and recovered to full range values, at 800MS/s and 500MS/s update rate, consuming around 780μW and 650μW in high speed and low noise comparators, respectively. This is equivalent to about 60% improvement in speed of the conventional single-stage comparator. Also, the amplitude of the control signals is reduced to about 18% of full range values, from 3.3v to 0.6v, by using the proposed low noise structure. High speed and low noise comparators can be implemented in 288μm2 and 480μm2 active area, respectively.

Robust Control of a Two-Terminal Cryogenic Current Comparator

Abstract: A digital $H\infty$ controller for a two-terminal cryogenic current comparator is designed. To this end, a set of mathematical models covering the actual system is proposed. Simulation results compare the open- and closed-loop systems based on the proposed controller and the traditional integral control. According to these results, the new controller can significantly reduce the noise in the superconducting quantum interference device sensor.

Implementation of CMOS charge sharing dynamic latch comparator in 130nm and 90nm technologies

Abstract: This paper proposes a CMOS charge sharing dynamic latch comparator along with the Buffer stage in 130nm and 90nm technologies. The supply voltage for this comparator is 1.3v and 0.9v for 130nm and 90nm respectively. Various analysis of different characteristics of the comparator such as offset, ICMR, propagation delay, power dissipation has been carried out in both the technologies and the result has been compared for both the technologies. The simulation results shows that speed of 1.33GHz and 0.47GHz was achieved with the power dissipation of 4.89mW and 167.32mW in 90nm and 130nm technologies respectively.

Design of High Speed and Leakage Tolerant CMOS Comparator in UDSM Technology

Abstract: In modern digital VLSI design, domino logic style circuits are widely used. The CMOS domino logic circuit dissipates very low standby power and exhibits less area. We design a comparator circuit which uses footed domino logic and also implement a current mirror circuit in the design, to enhance the speed of the comparator. This paper emphasizes a CMOS comparator design to detect full match or mismatch of the binary input. The proposed design consumes low leakage power and had a higher speed, than other circuit. The delay, leakage power and average power of the proposed CMOS Comparator circuit have also been calculated and then it is compared with the Footed Domino Logic Comparator circuit with same parameter. The circuit has been simulated in 45nm CMOS technology on Cadence Tool for high fan-ins (4, 8, 16, 32& 64 bits).

Intrinsic comparator delay for output clamping circuit

Abstract: A circuit includes a comparator to generate a clamp output signal by monitoring an output voltage and a reference voltage that sets a clamp voltage threshold for the output voltage. The clamp output signal is employed to limit an input voltage from exceeding the clamp voltage threshold. A first switch supplies the reference voltage to the comparator. The first switch forms a portion of an intrinsic delay circuit with a first feedback path in the comparator to mitigate ripple in the output voltage. A second switch is coupled to the input voltage and a second feedback path in the comparator. The second switch forms another portion of the intrinsic delay circuit with the first switch, the first feedback path, and the second feedback path in the comparator to further mitigate ripple in the output voltage.

Analog-digital converter, solid-state image sensor, and electronic apparatus

Abstract: An analog-digital converter includes: a first comparator configured to make a comparison between a pixel voltage and a first reference voltage, the pixel voltage being a signal voltage outputted from a pixel including an photoelectric conversion element, the pixel voltage corresponding to electric charge generated by the photoelectric conversion element; a second comparator configured to make a comparison between the pixel voltage and a second reference voltage; and a voltage follower configured to connect an input terminal for the first reference voltage of the first comparator and an input terminal for the second reference voltage of the second comparator through a switch.

Systems and methods for compensating the input offset voltage of a comparator

Abstract: Systems and methods of actively compensating for the input offset voltage of a comparator are provided. A compensation circuit may include a compensation comparator for comparing the comparison signal generated using the output signal of a comparator, to a reference voltage. A first voltage accumulator is coupled to the compensation comparator and produces a first voltage that is related to a first amount of time that the comparison signal spends above the reference voltage. A second voltage accumulator is coupled to the compensation comparator, and produces a second voltage that is related to the second amount of time that the comparison signal spends below the reference voltage. The first voltage and/or the second voltage may be used to provide one or more compensation signals to one or more of the two input terminals of the comparator.

A SiGe 8-channel comparator for application in a synthetic aperture radiometer

Abstract: We present a high-speed low-power 8-channel comparator tailored for the application of sampling antenna signals in a cross-correlator system for space-borne synthetic aperture radiometer instruments. Features like clock return path, perchannel offset calibration and bias current tuning make the comparator adaptable and gives the possibility to adjust the comparator for low power consumption, while keeping performance within the requirements of the cross-correlator system. The comparator has been implemented and fabricated in a 130-nm SiGe BiCMOS process. Measurements show that the comparator can perform sampling at a rate of 4.5 GS/s with a power consumption of 48 mW/channel or 1 GS/s with a power consumption of 17 mW/channel.

A 3GHz Low-offset Fully Dynamic Latched Comparator for High-Speed and Low-Power ADCs

Abstract: In this paper, performances of various types of dynamic latched comparators are compared in terms of their offset voltages, speed and power. The accuracy of comparators, which is defined by its offset, along with power consumption, speed is of keen interest in achieving overall higher performance of ADCs. This can be achieved by the fully dynamic latched comparator which is proposed in this paper. This comparator shows 14.6mV offset which is small when compared to other dynamic comparators and pre- amplifier based comparators. This comparator not only achieves low-offset but also exhibit high-speed and low power in its operation, which can be used for low power high speed ADC applications. In this paper, we present a new dynamic latched comparator which shows lower input-referred latch offset voltage and higher load drivability than the conventional dynamic latched comparators. Even though numbers of transistors in the proposed comparator are more but overall area is small when compared to conventional dynamic latched comparators. This paper is organized as follows. Section II provides an overview of the various types of dynamic latched comparators in terms of their advantages and drawbacks, and section III describes the offset analysis of proposed dynamic latched comparator. Section IV provides schematics of various types of dynamic latched comparators which are drawn in T-Spice. Simulation results from HSPICE using 90nm PTM technology with VDD=1V and their comparisons are presented in Section V and conclusion is drawn in Section VI.

A 40 nm LP CMOS self-biased continuous-time comparator with sub-100ps delay at 1.1V & 1.2mW

Abstract: A fully differential continuous-time comparator, that consists of a preamplifier-latch cascade, achieves propagation delays of 99 ps for a 50mVpp and 74 ps for a 100mVpp input signal amplitude under 1.1V supply and 1.2mW power consumption. The comparator is completely self-biased thus reducing influence of PVT variations and eliminating the need for a voltage reference. Dynamic delay-power management is supported through digital programmability of the self-biasing and supply voltage scaling. The design occupies 0.0007mm2 in 40 nm LP CMOS process.

A low offset comparator for high speed low power adc

Abstract: A novel low offset, high speed, low power comparator architecture is proposed in this paper. In order to achieve low offset, both offset cancellation and dynamic amplifier techniques are adopted. Active resistors are chosen to implement the static amplifier circuit to obtain reduction in equivalent input referred offset voltage as well as to increase the circuit speed. The comparator is designed in TSMC 0.18 μm CMOS process. Monte Carlo simulation shows that the comparator has the offset voltage as low as 0.3 mV at 1 sigma at 250 MHz while dissipates 342 μW from a 1.8 V supply.

A novel, high speed window comparator circuit

Abstract: Circuits with voltage hysteresis properties are often utilized in systems operating under noisy input conditions. A very simple window comparator circuit is described in this paper, which can be used in low voltage and fast varying input conditions. The proposed circuit was simulated using LTspice-IV and experimental results are presented.

A low propagation delay dispersion comparator for low cost level-crossing ADCs

Abstract: This paper presents a low delay dispersion comparator for low cost level-crossing Analog-to-Digital converters. The conventional comparator circuit is modified by adding a variable driving-current block (VDCB) which is used such that it supplies the output node of the differential amplifier with a current that is inversely proportional with the level of input signal. The modification incurs small area overhead (only three transistors) compared with the previous works. The proposed comparator is designed in order to reduce the propagation delay dispersion caused by variable input overdrive and the common mode level. The proposed circuit is implemented in 130nm technology. The simulation results show that the overdrive-related propagation delay dispersion of the proposed technique is 27% of its counterpart in the conventional comparator for an input frequency up to 600MHz. The active area of the technique140.2 μm2 and the power consumption is 250 μW at 200MHz.

A novel CC-II based current comparator and its application as current mode flash ADC

Abstract: In this paper, a new design for current comparator based on Current Conveyor-II (CC-II) is proposed. The proposed current comparator utilizes the concept of positive feedback. Simulations have been performed on Pspice using 0.18um CMOS technology with 1.8V supply. Final results confirm a fairly quick response, less power dissipation and a resolution of 4.4uA for the current comparator. A 2-bit current mode flash ADC is designed using the proposed comparator.

A 0.5V 200MHz offset trimmable latch comparator in standard 0.18um CMOS process

Abstract: This paper presents a new high-speed, ultra low-voltage dynamic latch comparator with rail-to-rail input range and an offset trimming technique. Low voltage constraints especially sub-1V applications make the conventional comparator circuits inefficient to operate with high-speed rate. To overcome this issue, a boosting technique has been utilized to increase the overdrive voltage of cross-coupled devices and so speed-up the regeneration phase. The Simulation results for the designed comparator in standard 0.18um CMOS process show that the comparator can detect 200uV input difference at 200MHz frequency while consumes 20.5uW in the latch and 8uW in the offset trimming blocks from a 0.5V supply.

Low Power Relaxation Oscillator

Abstract: A relaxation oscillator circuit includes a comparator including a first input, a second input, a bias input, and an output. The first input is coupled to a charging node, and the second input is configured to receive a reference voltage. The relaxation oscillator circuit further includes a first bias circuit configured to provide a bias signal to the bias input of the first comparator when a first node voltage on the charging node exceeds a first reference.

Circuits and methods for constant output current in a flyback converter

Abstract: Flyback converters are disclosed herein. An embodiment of a flyback converter includes a transformer having a primary side and a secondary side. A switch is connected to the primary side of the transformer, wherein the switch controls the current in the primary side of the transformer. A resistance is connected between the switch and a common node. The converter also includes a comparator having a first input and a second, the first input being connected between the switch and the resistor. Driver logic controls the state of the switch, wherein the output of the comparator is coupled to the driver logic. A voltage source is connected to the second input of the comparator. An error amplifier compares the voltage at the second input of the comparator to an adjustment voltage, the output of the error amplifier is coupled to the driver logic.

Research on High Accuracy Current Comparator and Self-Calibration Methods

Abstract: This paper introduces the structure and the working principle of a high-accuracy current comparator. This paper also indicates the primary source of error: the leakage capacitance coupling current between the turns of the secondary winding. In order to reduce this error, the secondary winding is wound with a coaxial cable. With good shielding, the error introduced by the connecting windings is minimized. This paper also presents a new self-calibration method for the 1:1 current comparator and an innovative design of the current comparator. The self-calibration method can also be used to calibrate multiratio current comparators with an uncertainty of less than $5\times 10^{-7}$ at a primary current ranging from 5 A to 2000 A.

Power monitoring circuitry

Abstract: Power monitoring circuitry. In some embodiments, comparator circuitry may be configured to receive a first voltage value and a second voltage value, and to identify the greater of the first and second voltage values. Selector circuitry coupled to the comparator circuitry may be configured to power one or more components within the comparator circuitry with a supply voltage corresponding to the greater voltage value. In other embodiments, a method may include identifying, via a comparator, the largest among a plurality of voltage values, and powering one or more logic components within the comparator with the identified voltage value.

Capacitive dynamic comparator with low kickback noise for pipeline ADC

Abstract: A kickback noise capacitive dynamic comparator is presented. The low kickback noise is achieved by controlling additional MOSFETs in signal path to cancel voltage variation in the internal node of comparator. A neutralization technique is also implemented into the proposed design to further reduce the impact of kickback noise in the inputs of comparator. By adapting both techniques, the kickback noise of the proposed dynamic comparator is reduced 23 times smaller compared to that of conventional implementation at 500mV differential input voltage and 250MHz operating speed. The design is implemented in TSMC 0.18-μm CMOS technology process with 1.8V power supply and consumes 44.5μw power dissipation.