Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Digital-to-pulse width converter utilizing a distributed pulse width

Abstract: A digital-to-analog converter includes a digital-to-pulse width converter that converts a desired digital set-point value to a corresponding signal having a pulse width indicative of the desired set-point value. The desired set-point value is fed to a comparator which compares that value to the current count value from a counter that is counting up in ascending integer order. However, instead of presenting the counter output signal lines to the comparator in a normal conventional manner wherein the count value of the counter is presented to the comparator in the conventional ascending integer order, the current value of the counter is presented to the comparator in other than a conventional ascending order. The result is a comparator output signal that transitions more than one time between binary logic levels. This effectively increases the frequency of the comparator output signal. An optimum connection of the counter output signal lines to the comparator can be achieved such that the comparator output signal is divided up into a series of binary logic level pulses that are distributed across the entire cycle time period of the counter. This results in a subsequent output of an integrator that has reduced ripple voltage amplitude.

Low current comparator with hysteresis

Abstract: An accurate, low-current integrated circuit comparator includes a differential input stage 10 comprising differential pair transistors 22 and 24, differential pair current mirror transistors 26 and 28, and a constant current source transistor 30. The comparator also includes an hysteresis stage 12 coupled to one of the current mirror transistors; the hysteresis stage comprises an hysteresis mirror transistor 34 and a switching transistor 36. The comparator additionally includes a gain stage 14 comprising a gain transistor 38 and a constant current source transistor 40. Finally, the comparator includes an output stage 15 comprising gain transistor 42 in an open-drain configuration. In the disclosed embodiment, the descending trip threshold is set entirely by the ratios of device geometries, and is therefore very accurate and is independent of temperature, lithography and processing variations. While the ascending trip threshold is related to the ratio of tail current of the differential pair to the transistor gain of the devices in that pair, which quantities are dependent on the device parameters, this relationship is only to the one-half power, and therefore is relatively small.

Voltage margin testing of a transmission line analog signal using a variable offset comparator in a data receiver circuit

Abstract: A data receiver circuit having a comparator that exhibits substantially variable offset that is controllable to represent a variable reference level, without a separate input to receive a reference voltage level. The comparator output provides an indication of the comparison between a fixed voltage level applied to its differential signal input and the variable reference level. While changing an offset code that is fed to an offset control input of the comparator, and while applying a fixed voltage level that represents a symbol in the transmission line analog signal, a value of the offset code which causes the output of the comparator to change states is captured. A similar process may be repeated for different symbol values that can be transmitted, such that an indication of the voltage margin may be obtained as a difference between two captured offset codes. Circuitry to perform the process may be provided on-chip to the receiver circuit.

An unshunted comparator as a device for quantum measurements

Abstract: The unshunted single-flux-quantum SFQ comparator is described for the first time. Its dynamic behavior is surprisingly similar to the familiar resistively-shunted SFQ comparator. For certain parameter ranges both junctions of the comparator may pulse at the same time to create a reflected anti-pulse. This phenomenon is utilized in a new SFQ comparator design with better coherence properties for qubit readout. Considerations of quantum noise for the unshunted SFQ comparator are discussed.

Hysteresis comparator circuit for operation with a low voltage power supply

Abstract: A hysteresis comparator circuit working with a low voltage supply and of a type which includes a composite structure incorporating first and second differential cells respectively comprised of an npn bipolar transistor pair with common emitters, on the one side, and a pair of pnp bipolar transistor pair with common emitters, on the other, such cells being coupled together through the bases of the respective transistors. The circuit includes at least one pair of variable current sources associated with each cell and tied operatively to the voltage value present on the comparator output; in addition, a voltage divider is connected between each interconnection of the bases of the transistors forming the cells.