Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling

Abstract: Successive approximation register (SAR)-based analog-to-digital converters (ADCs) are provided that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. An SAR ADC (100) can include a window circuit (138) that provides the comparator output directly from the comparator (120) to the DAC (140) before the latching time of the comparator (120). After the latching time, the latched version of the comparator output is provided to the DAC capacitor (144). By providing the capacitor output to the DAC capacitor (144) before latching, the DAC capacitor (144) can settle earlier compared to the SAR ADC (100) where the DAC capacitor (144) settling begins after the latching time of the comparator (120).

Current sensor circuit

Abstract: A current sensor circuit for measuring by means of a Hall element the magnitude of a magnetic flux obtained in response to an input electric current and for generating a signal corresponding to the result of measurement, wherein a Hall element (2) is driven by a voltage obtained by a voltage follower-type voltage generating unit (4) whose output voltage changes by following a supply voltage, and the voltage obtained by the voltage generating unit is applied as an offset compensating voltage, thereby simplifying the circuit of a Hall element portion. In addition, a forward threshold voltage and a reverse threshold voltage that are used in a forward comparator unit (6) and a reverse comparator unit (8), respectively, are separately generated by a first reference resistor unit (5) and a second reference resistor unit (7), thereby simplifying an adjustment operation at a comparator portion and improving the comparator accuracy.

Phase comparator using two capacitors alternately charged via constant current sources

Abstract: One of two capacitors in a phase comparator is discharged for a logic zero data input and is alternately charged with opposite polarities, depending on the state of a regenerated clock signal, for a logic one data input. The resultant charge of the capacitor when the data input again becomes zero is used to control a variable frequency oscillator which produces the clock signal, while the other of the two capacitors is discharged and then charged in the same manner. A phase locked loop including the phase comparator can accommodate arbitrary data sequences of a return-to-zero data signal and does not require a low pass filter.

Voltage comparator with floating gate MOS transistor

Abstract: This invention relates to a voltage comparator with an input for an analog signal and an output for a digital signal, comprising an inverter which has an input coupled to the comparator input and an output coupled to the comparator output, and comprising at least two MOS transistors coupled to each other, at least one of the two MOS transistors being of the floating gate type.

Circuits and methods with comparators allowing for offset reduction and decision operations

Abstract: Circuits and methods may be improved by using ADCs that compensate for the effect of comparator input offset on comparator decisions. Offset compensation may be implemented in an ADC by using an amplifier section between the input of the ADC and a comparator section of the ADC to amplify the signals supplied to the comparator inputs and thereby reduce the effect of comparator offset on the comparator decision. The comparator section may be an autozeroing comparator section that is capable of performing an offset reduction operation to store offset compensation values at capacitors provided at its inputs. The amplifier section may be an autozeroing amplifier section having one or more amplifier stages that are capable of performing an offset reduction operation to store offset compensation values at capacitors provided at their inputs. Offset compensation may also be implemented using an autozeroing comparator section without a preceding amplifier section.