Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Comparator and a/d converter

Abstract: In a comparator for use in a parallel A/D converter, the comparator (100) is provided with reset transistors (mra, mrb). When the comparator (100) is in reset state, the PMOS transistors (mra, mrb) are provided with the inverted signal /CLK of a clock signal and the voltages at two internal nodes (Va, Vb) becoming a differential pair are reset forcibly to a predetermined reset voltage by the reset transistors (mra, mrb). The inverted signal /CLK of a clock signal is generated with a predetermined time lag. When the comparator (100) is in reset state, reset release timing of the internal nodes (Va, Vb) is delayed behind the comparison operation timing of the comparator. Consequently, even if the frequency of the clock signal and the frequency of an analog input signal are increased, voltage balance is improved at the internal nodes forming a differential pair when the comparator is in reset state, and voltage comparison precision is enhanced.

Comparator and analog-to-digital converter

Abstract: A comparator for an analog-to-digital converter having a tri-state inverter provided on the side where an input of a data register section is located, wherein the need for a switch on the input side in the data register section is eliminated to allow reduction of the number of components used in a comparator, and the flow-through current of the tri-state inverter can be reduced significantly by operating the tri-state inverter as a common inverter after making outputs from the comparator stable.

Pre-amplifier design for high-speed analog-to-digital converters

Abstract: The present invention overcomes the gate leakage drawback existing in advanced CMOS technologies to achieve extremely high-speed analog-to-digital conversion. The circuit and method employ an input offset storage (IOS) technique to calibrate the differential comparator device during an auto-zero cycle. The reference voltage and offset voltages are stored on capacitors coupled to the inputs of the differential comparator device during the auto-zero cycle. A source follower is placed between each capacitor and the inputs to the differential comparator device. The source followers are selected to prevent leakage from the capacitors during a conversion mode. Additionally, switches utilized in feedback loops for auto-zeroing the differential comparator are also selected to prevent leakage of the capacitors in the conversion mode.

A Novel 1GSPS Low Offset Comparator for High Speed ADC

Abstract: In high speed ADC, comparator influence the overall performance of ADC directly. This paper describes an ultra high speed and low offset preamplifier-latch comparator. The comparator use two negative resistors parallel with positive resistors as load resistors of preamplifier to improve its gain so as to reduce offset voltage. Meanwhile, the comparator uses a novel method to reduce the recovery time of regenerative stage by add a pre-set quiescent current. Based on TSMC 0.18um CMOS process model, simulated results show the comparator can work under ultra high speed clock frequency 1GHz. The comparator has a low offset voltage (0.9mv), a short fall delay time (60ps) and rise delay time (50ps). With 1V swing, it is suitable for 10bit 1GSPS high speed ADC.

Circuit for monitoring of loads

Abstract: A circuit is described for monitoring of loads having measuring resistors in the load circuit. The circuit evaluates the measuring voltage drops obtained at the measuring resistors. The circuit comprises at least one comparator stage made up of a reference current section and a comparator section. A temperature-dependent reference current is formed in the reference current section and supplied to the comparator section, with the temperature-dependent reference current comprising a voltage-independent component and a voltage-dependent component. The comparator section comprises one or more input branches, corresponding comparator branches, and a reference branch. The comparator branch compares the reference current flowing in the reference branch with the input currents flowing in the input branches and representing a measure for the measuring voltage drops obtained at the measuring resistors and applied to the inputs of the comparator stages. Depending on this comparison, a certain voltage level is emitted at the outputs of the comparator stages.