Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Capacitor coupled current mode balance circuit

Abstract: A control circuit is provided for controlling the on-time of a pair of switching transistors in a half bridge converter. The control circuit includes a first comparator for comparing the converter output voltage with a reference voltage. The control circuit also includes a circuit which generates a first signal indicative of the current through the primary winding of the converter output transformer. Also included is a circuit which generates a second signal indicative of the on-time of one of the switching transistors exceeding the on-time of the other switching transistor. The first and second signals are averaged and compared with the output voltage of the first comparator by a second comparator. The second comparator controls the on-time of the switching transistors. In this way, any imbalance in the on-time of the switching transistors is corrected by the control circuit.

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Abstract: We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 25-bit to 705-bit The ADC is manufactured in a 90 nm CMOS technology, with a core area of 085 mm × 035 mm, a 12 V supply for the core and 18 V for the input switches It has an effective number of bits (ENOB) of 705-bit, and a power dissipation of 85 mW at 60 MS/s

DC-DC converter and control circuit with low-power clocked comparator referenced to switching node for zero voltage switching

Abstract: Disclosed examples provide DC-DC converters and control circuits to provide high and low-side driver signals and to selectively adjust a delay time between a low-side switching device turning off and a high-side switching device turning on according to a comparator signal, including a clocked comparator circuit referenced to a switching node to sample the voltage across the high-side switching device in response to a first edge of the high-side driver signal, and to generate the comparator signal indicating a polarity of the sampled high-side switch voltage to facilitate zero voltage switching of the high-side switching device.

Driver having inductance-controlled current slew rate

Abstract: A control system for minimizing and controlling the current slew rate of an output device by using inductance to directly measure the current slew rate is provided. The control system may, for example, be used to control and minimize the current slew rate through signal drivers and allow for faster drivers and/or larger numbers of drivers on integrated circuit chips. In accordance with one embodiment of the invention, an inductor is serially coupled with an output device. A predriver is coupled to the gate of the output device for providing a voltage slew rate at the output device gate. A comparator is coupled to the inductor for sensing a voltage indicative of a current slew rate through the inductor and outputing a signal indicating whether the current slew rate exceeds or falls below a desired level. A controller responsive to the comparator is provided for controlling the driver to increase and decrease the voltage slew rate at the output device gate when the comparator signal indicates that the current slew rate respectively falls below and exceeds the desired level, thereby controlling the current slew rate through the inductor and through the output device.