Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Switched power supply with voltage regulator having pwm with hysteretic loop controller and method for operating and using same

Abstract: A switched power supply (40) has a pulse width modulator to adjust a pulse width that controls the output voltage (104). The width modulator includes a comparator (66) that compares a signal (104) indicating a value of the power supply to a ramp wave (69). An output of the comparator (66) is a signal containing a time width proportional to the output of the power supply. Additionally, a first comparator (90) compares the output voltage (42) to a first reference voltage (94). When the output voltage (42) exceeds the first reference voltage (94), the first comparator (90) changes state. A second comparator (88) compares the output voltage (42) to a second reference voltage (92). When the second reference voltage (92) exceeds the output voltage (42), the second comparator (88) changes state. The pulses are width modulated to first or second width limits in response to changes of output states of the first and second comparators.

Self-limiting pulse width modulation regulator

Abstract: A self-adjusting PWM regulator which minimizes undershoot and overshoot conditions is disclosed. The regulator includes a charge pump, a voltage comparator circuit, and a latch circuit. The input of the voltage comparator circuit includes an output of the charge pump. The input of the latch circuit includes an output from the voltage comparator circuit. The latch circuit includes a pair of SR latches coupled to a pair of AND/OR gates. The latch circuit transmits a first signal to the charge pump to prevent an overshoot condition if the output from the voltage comparator circuit is in a first state, and transmits a second signal to prevent an undershoot condition if the ouput from the voltage comparator circuit is in a second state. This keeps the charge pump adjusted within the limits of its control.

Design of high speed and low power 4-bit comparator using FGMOS

Abstract: This paper presents a novel low power and high speed 4-bit comparator extendable to 64-bits using floating-gate MOSFET (FGMOS). Here, we have exploited the unique feature of FGMOS wherein the effective voltage at its floating-gate is the weighted sum of many input voltages which are capacitively coupled to the floating-gate. The performance of proposed 4-bit comparator circuit has been compared with other comparator circuits designed using CMOS, transmission gate (TG), pass transistor logic (PTL) and gate diffusion input (GDI) technique. The proposed FGMOS based 4-bit comparator have shown remarkable performance in terms of transistor count, speed, power dissipation and power delay product besides full swing at the output in comparison to the existing comparator designs available in literature. Thus the proposed circuit can be viable option for high speed and low power applications. The performance of the proposed FGMOS based 4-bit comparator has been verified through OrCAD PSpice simulations through circuit file/schematics using level 7 parameters obtained from TSMC in 0.13 μm technology with the supply voltage of 1 V.

Cache tag comparator with read mode and compare mode

Abstract: A cache TAG, which has a compare mode, an and/or/invert mode, and a read mode, has a programmable comparator which receives an external data signal and an output from an array of memory cells and provides an output to a secondary amplifier. The secondary amplifier provides an output to a match comparator in the compare mode and the and/or/invert mode and to an output buffer in the read mode. The programmable comparator is programmable according to the mode of the cache TAG. The compartor uses selectively enabled transmission gates which provide minimal delay in providing the appropriate data to the secondary sense amplifiers.

A CMOS Voltage Comparator with Rail-to-Rail Input-Range

Abstract: A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 μm×221 μm in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).