Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Circuit arrangement for generating a digital clock signal

Abstract: A circuit arrangement for generating a digital clock signal which manages without a crystal oscillator and has a low current consumption. The circuit arrangement includes: a transistor circuit having a first, n-channel FET transistor and a second, p-channel FET transistor, which are connected in series, a comparator having a positive comparator input, a negative comparator input and a comparator output, a device for providing two switching thresholds to the negative input of the comparator, and a capacitance, which is alternately charged and discharged via the two FET transistors. The voltage present at the capacitance is fed to the positive comparator input, and the output voltage of the comparator, which represents a digital clock signal, is fed back to the input of the device for providing two switching thresholds and to the gate terminals of the first and second FET transistors.

Detection circuit for a video tape recorder signal

Abstract: A detection circuit for a video tape recorder signal on the input of a TV set connected to a line synchronization separating circuit (11) in turn connected to a PLL (12) comprises a first phase comparator (15), the PLL (12) exhibiting a first time constant (I1, C1) corresponding to an operation on a normal TV signal. This circuit further comprises a switch (20) for switching the PLL on a second time constant (3I1, C1) shorter than the first one, a second phase comparator (22) for comparing the input and output phases of the first phase comparator, the second phase comparator being associated with a third time constant (I2, C2) shorter than the first and second ones, a threshold comparator (24) supplying to the switch (20) a control signal when the comparator output (22) is outside determined limits.

Dual polarity, high input voltage swing comparator using MOS input transistors

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Replica driver mismatch correction using a variable offset comparator

Abstract: A number of data symbols are driven into a transmission line while simultaneously driving the data symbols into another node. A difference between a signal level from the transmission line and a signal level from the other node while driving the symbols is determined. The difference is applied to a signal input of a variable offset comparator. One of a number of binary values (offset codes) are applied to an offset control input of the comparator, to adjust an implied, variable reference level of the comparator, prior to the comparator performing a comparison between the input signal and the implied reference level.

Schaltungsanordnung zur Anpassung eines aktiven Sensors an eine Auswerteschaltung

Abstract: A circuit arrangement is disclosed which permits connection of an active sensor (1) in the form of a binary current source to an electronic evaluation circuit (3) designed for use with a passive sensor. The electronic evaluation circuit (3) comprises a comparator (4) which produces a signal proportional to the speed (revs.) and a window comparator (6, 7) with which the functioning of the sensor (1) can be monitored. The voltage signal applied to the comparator (4) is produced by a resistor (R1) connected in series with the active sensor (1) and with a voltage divider (R2, R3) which is connected in parallel with the active sensor. The voltage signal is led to the N input of the comparator (4) via an RC element (R4, C1) and to the P input of the comparator (4) directly, thus ensuring that the comparator responds to fluctuations at the central tap (M) of the voltage divider. This circuit is not sensitive to fluctuations in the intensity or voltage of the supply current or to drift in the active sensor.