Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

A 0.5 V offset cancelled latch comparator in standard 0.18 μm CMOS process

Abstract: This paper presents a new 0.5 V high-speed dynamic latch comparator with built-in foreground offset cancellation capability and rail-to-rail input range. Traditional latch comparators lose their speed performance in low voltage condition, especially in sub-1V applications. The proposed latch comparator utilizes a speed-up technique based on a novel boosting method to mitigate the low voltage imperfections on circuit operation. Employing a new offset cancellation technique based on the same boosting capacitors is another key idea. This enhances the accuracy of the ultra low-voltage latch comparators and relaxes the need for preamplifier stage, which is conventionally used in the low offset latch comparator. The performed Monte Carlo simulations over corners in 0.18 μm standard CMOS process show the improvement of input referred offset voltage with a standard deviation of 29.9 mV/299 μV before and after offset cancellation, respectively. The designed comparator dissipates 34 μW power from 0.5 V voltage supply while operating in 200 MHz clock frequency and detects 1 mV input difference.

Successive approximation type a/d converter circuit

Abstract: A successive approximation type A/D converter circuit includes a comparator circuit which determines which of an input analog voltage and a comparison voltage is larger, a register which successively takes in and stores a comparison result, and a local DA converter circuit which converts a register value into a voltage to generate the comparison voltage. The comparator circuit includes amplifier stages and a feedback capacitor connected to an input terminal of one of the amplifier stages, takes in an analog voltage during a first period, receives a input voltage depending on a potential difference between the analog and comparison voltages and amplifies the input voltage in the amplifier stage during a second period, and applies positive feedback to an input terminal of a corresponding amplifier stage via the feedback capacitor so as to impart a hysteresis of 1 LSB or less when an output of the comparator circuit changes.

Low power transponder circuit

Abstract: A low power transponder circuit comprises two comparator (62, 104 ; 64, 106) coupled to a signal input section, wherein only a first comparator (62, 104) is active before a valid wake-up signal is detected and validated. The first comparator (62,104) consumes less power than the second comparator (64, 106), and the second comparator (64, 106) operates at a higher speed than the first comparator (62, 104), such that valid received signal processing is performed on a signal from the second, higher speed comparator (64, 106). Reference voltage levels for the two comparators can also be modified during circuit operation with either information stored in the transponder or by data received in a valid received signal.

Low-current oscillator with hysteresis input buffer

Abstract: A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.

Investigation of the relationship between the gray zone and the clock frequency of a Josephson comparator

Abstract: The Josephson comparator is one of the fundamental building blocks of rapid single flux quantum (RSFQ) electronics. Within this circuit family it is the exclusive device which provides logical data processing. The Josephson comparator is also the basic decision element for very fast analog-to-digital converters and sampler circuits for low input power and high-bandwidth signals based on the RSFQ technique. The performance of those devices is fundamentally determined by the characteristics of the Josephson comparator. In this study the gray zone dependency on the clock frequency of a Josephson comparator is investigated by simulations concerning the influence of thermal noise. This investigation is performed for a series of operating points defined by the bias current and different noise levels defined by the operating temperature. In contrast to former investigations, we analyzed the comparator embedded in a realistic environment for output data processing. We identified a characteristic clock frequency fc for a comparator topology designed for a 1 kA cm −2 niobium fabrication technology. The gray zone of 8 μA remains constant for clock frequencies below fc = 15 GHz and starts to increase for larger frequencies. We also found out that this characteristic frequency is independent of the intensity of thermal noise and therefore independent of temperature. (Some figures in this article are in colour only in the electronic version)