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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


Papers
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Patent
22 Jul 1999
TL;DR: In this article, a low-power differential comparator is proposed, where the input stage bias is used not only to set a bias level but also to set the hysteresis level of the differential comparators.
Abstract: A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator circuit are referred to ground to reduce the total DC current draw, e.g., by a factor of 7. The multiple use of the input stage bias and grounded connections to the positive and/or negative inputs reduce the overall current requirements of the differential comparator circuit substantially while maintaining full operating speed as compared to conventional differential comparator circuits. In one embodiment using the low power differential comparator circuit, a clock receiver implements hysteresis which is relatively independent from variations in environmental factors such as temperature, and from power supply variations. In this embodiment, the input stage of a low power comparator circuit is biased by the output of a bias circuit. The bias circuit, which in the disclosed embodiment is a regulated current source, may be started-up with the output of a start-up circuit if desired. In operation, when the temperature increases the bias current decreases, but the values of hysteresis resistors in the low voltage comparator also increase. Therefore, the resultant hysteresis value does not change appreciably.

11 citations

Patent
23 Mar 2004
TL;DR: In this paper, a re-generated comparator coupled to a common mode node of the pre-amplifier is used to adjust the output common mode of the adaptive amplifier.
Abstract: The circuit with adaptive amplifier output common mode voltage adjustment includes: a differential pre-amplifier; a re-generated comparator having a differential input coupled to a differential output of the pre-amplifier; and a replica comparator coupled to a common mode node of the pre-amplifier for adjusting a common mode of the pre-amplifier. The replica comparator provides a trip-point reference to set the output common mode of the pre-amplifier. This sets the output common mode of the pre-amplifier to the most sensitive region of the re-generated comparator.

11 citations

Proceedings ArticleDOI
01 Sep 2006
TL;DR: In this paper, a comparator with the capability of high decision speed, but static power consumption was avoided, and the circuit implements a technique to enhance resolution while keeping the ability of a high switching speed.
Abstract: This paper presents a comparator with the capability of a high decision speed, but static power consumption was avoided. Furthermore the circuit implements a technique to enhance resolution while keeping the ability of a high switching speed. During the reset phase the comparator is pulled to ground level, which defines a logic voltage level. A test chip with the comparator was manufactured in a 120nm CMOS technology with a supply-voltage of 1.5V. For a bit-error-rate (BER) of 10-9 the presented comparator is able to detect 11.2mV at 2GHz, 20mV at 3GHz, 26mV at 3.5GHz and 118mV at 4GHz. The power consumption was 788muW at 3.5GHz and 812muW at 4GHz

11 citations

Patent
04 Dec 2013
TL;DR: In this article, an integration circuit including a first capacitor is operatively coupled to a comparator, and the comparator is configured to compare a first capacitance voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison.
Abstract: An integration circuit including a first capacitor is operatively coupled to a comparator. The comparator is configured to compare a first capacitor voltage of the first capacitor to a reference voltage and produce a first comparator output based on the comparison. A current generator is operatively coupled with the integration circuit and configured to balance charge on the first capacitor. A control unit is operatively coupled to the comparator and the current generator and configured to balance charge on the first capacitor by sensing the first comparator output and controlling the current generator based on the first comparator output.

11 citations

Patent
09 May 2000
TL;DR: In this article, a comparator which can operate stably against an absolute value distribution of a threshold voltage among MOS transistors and has a wide allowable range against the threshold voltage dispersion and besides allows reduction in power consumption is presented.
Abstract: A comparator which can operate stably against an absolute value distribution of a threshold voltage among MOS transistors and has a wide allowable range against the threshold voltage dispersion and besides allows reduction in power consumption. The comparator employs a single MOS transistor, and a resistance element is connected between the drain electrode of the MOS transistor and a power supply. A capacitor is connected between the gate electrode of the MOS transistor and a dc potential point, and a switch is connected between the gate electrode and the drain electrode. A comparison reference level and comparison input data are inputted in a time series to the source electrode of the MOS transistor, and the MOS transistor performs a comparation operation.

11 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100