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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


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Patent
08 Mar 1996
TL;DR: In this article, a drive amplifier is coupled to the valve actuator 20 and this is supplied by a voltage Uver and receives the output Uaus of a comparator, which operates on a triangular waveform reference T and the command variation signal delta W.
Abstract: The circuit has a drive amplifier 10 coupled to the valve actuator 20 and this is supplied by a voltage Uver and receives the output Uaus of a comparator. The comparator operates on a triangular waveform reference T and the command variation signal delta W. The output is fed back via an impedance converter 30. If the output is the same as the comparator supply Uelek then the feedback is independent of the drive supply Uver. If the output is zero the feedback is also zero

10 citations

Patent
24 Jun 2005
TL;DR: In this article, a comparator-based driver has a configurable inverter that inverts one of the comparator output signals for application to the gate of a driver transistor used to generate the driver output signal.
Abstract: A comparator-based driver has a configurable inverter that inverts one of the comparator output signals for application to the gate of a driver transistor used to generate the driver output signal. The configurable inverter can be selectively configured to provide any one of at least two different inverter logic threshold levels. In one possible operational scenario, the configurable inverter is configured such that the inverter logic threshold level is equivalent to the comparator's differential common-mode voltage to provide relatively high driver symmetry. The configurable inverter is then configured to provide a different inverter logic threshold level that is greater than the comparator's differential common-mode voltage to inhibit chattering in the driver output signal.

10 citations

Proceedings ArticleDOI
21 Nov 2004
TL;DR: By making the comparator self-testable hence the potential problem of a faulty comparator circuit during test mode operation is greatly reduced, the design effort already spent in providing an effective means of testing SOCs is leveraged.
Abstract: In this paper, a novel full range window comparator with self-testability feature is presented. The use of a mixed-signal full range window comparator for built-in-self-test (BIST) of analogue cores in system-on-chip (SOC) was described in. Therefore we leverage on the design effort already spent in providing an effective means of testing SOCs, by making the comparator self-testable hence the potential problem of a faulty comparator circuit during test mode operation is greatly reduced.

10 citations

Patent
17 Jun 1977
TL;DR: In this paper, an analog-to-digital converter includes a first comparator which receives an analog input, and a voltage subtractor circuit which produces an output voltage which represents the voltage difference between a first boundary of the voltage gap which encompasses the analog input voltage and the value of the analogue input voltage.
Abstract: An analog-to-digital converter includes a first comparator which receives an analog input. The first comparator generates a plurality of reference voltages which establish a first continuous range of voltage gaps. The first comparator has a plurality of quantizing outputs, one of which will be at a logical one and the rest of which will be at logical zeros in order to indicate which of the voltage gaps encompasses the analog input voltage. The first comparator also has a reference current output whose magnitude is representative of which voltage gap encompasses the analog input voltage. A first encoder receives the quantizing outputs of the first comparator and generates a binary number which represents which of the voltage gaps the analog input voltage is encompassed by and which constitutes the most significant bit group of the binary digital representation of the analog input voltage. A voltage subtractor circuit receives as inputs the reference current output of the first comparator and the analog input. The voltage subtractor produces an output voltage which represents the voltage difference between a first boundary of the voltage gap which encompasses the analog input voltage and the value of the analog input voltage. The voltage subtractor output voltage is produced concurrently with the action of the first encoder, thereby providing overlapping operations for increased conversion speeds. This voltage is provided as an input to a second comparator which compares the output voltage produced by the voltage subtractor with a plurality of internal reference voltages which form a second continuous range of voltage gaps. The second comparator has a plurality of outputs, one corresponding to each of the voltage gaps encompassed by the reference voltages in the second comparator. The second comparator produces a logical one on an output corresponding to the particular voltage gap which encompasses the difference voltage produced by the voltage subtractor. A second encoder receives as inputs the outputs of the second comparator and generates a binary output which represents the difference voltage produced by the voltage subtractor and which constitutes the least significant bit group of the analog input voltage. In combination, the output of the first encoder and the output of the second encoder form a binary digital representation of the analog input voltage, including the most significant bits and the least significant bits thereof.

10 citations

Patent
Jimmy Yee1
25 Jul 1985
TL;DR: In this paper, a sensor input terminal is biased to a level between the reference levels of the comparators, but varies to outside the window in response to current flowing from or into the sensor terminal.
Abstract: An electronic circuit for interfacing a sensor of either current sourcing or current sinking type to a data bus requiring signals of predetermined characteristics, the circuit including first and second level comparators set to different reference levels so as to define a window between the reference levels at which neither comparator is actuated. A sensor input terminal is biased to a level between the reference levels of the comparators, but varies to a level outside the window in response to current flowing from or into the sensor terminal. The comparator output terminals are connected to an output circuit which produces a signal suitable for transmission on the data bus in response to actuation of either comparator.

10 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100