Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET

Abstract: A novel latch-based comparator is proposed for Successive Approximation (SA) Analog to Digital Convertor(ADC) with sub-32nm Double Gate MOSFETs(DG-MOSFET). The regeneration time of the latch is improved by using an extra positive feedback which uses the threshold voltage modulation property of DG-MOSFET. Simulation of the proposed comparator with CEA-LETI's DG-MOSFETmodels resulted in a delay of 25ps. The average power dissipation over one clock period is ≤ 1μW up to the clock frequency of 100MHz, which increases as frequency is increased resulting in an average power of 6.54μW at 1GHz, for an input voltage differential of 50mV.

Dynamic biasing circuit for continuous time comparators

Abstract: A method for dynamically adapting the biasing current for a fast switching CMOS comparator is achieved. The difference of the two input signals of said comparator controls the comparator's biasing current, where the biasing current is high only when the difference is low and the comparator's switching is likely to happen and where the biasing current is kept low at other times. In a current mirroring circuit, the voltage difference at the comparator inputs controls the mirroring ratio. The biasing current reaches its maximum when the input voltage difference approaches zero. Once the input voltage difference crosses zero and continues to change in the same direction as before, that is after the polarity of the voltage difference changed, the control mechanism alternates the connection of the comparator input signals to the current controlling elements, in order to now reduce the current with a further increase of the voltage difference. The same circuit can have opposite characteristics, providing a minimum current when the input voltage difference is low, by reversing the connection of the inputs to the current controlling elements. An alternative circuit is described, that does not need said alternating mechanism.

Comparator circuits having non-complementary input structures

Abstract: A non-complementary comparator includes an evaluation element such as a memory cell, a differential amplifier, or another type of circuit capable adapted to perform an evaluation function, and at least first and second input legs each coupled to a corresponding one of a first and second node of the evaluation element. The first and second input legs have non-complementary structures relative to one another, with each of the non-complementary structures having associated therewith a variable parameter, e.g., a variable resistance, variable current or variable voltage, having a value that is a function of a corresponding input signal. The evaluation element performs a comparison of at least first and second inputs applied to the respective first and second input legs. The input legs may each be implemented as a weighted array of transistors, with each of the transistors in the weighted array associated with a given leg corresponding to a particular bit or other portion of an input signal applied to that leg. The non-complementary comparator may be used as a multi-digit comparator to determine the relative weight of digital words, or to implement other comparator circuits such as, e.g., majority rule circuits, analog common mode comparators, greater than/less than circuits, array addition and comparison circuits, serial adder-binary search (SA-BS) circuits, analog adders, add-compare-select (ACS) circuits, coupled memory cell comparators, and comparators with mask functions.

Presettable single-input voltage-time integrator

Abstract: A timing circuit capable of operation from a single-input waveform, comprising an integrator circuit which includes: (1) a series resistor-capacitor (R-C) combination, one end of the resistor of the R-C combination comprising the input to the timing, and integrator, circuit; (2) an operational amplifier connected across the capacitor of the R-C combination, the amplifier serving to integrate the single-input waveform; and (3) a metal-oxide, semiconductor, field-effect transistor (MOSFET), serving as a switch, connected across the operational amplifier, the source of the MOSFET switch being connected to the input of the operational amplifier, at the junction of the R-C combination, the drain of the MOSFET switch being connected to the output of the operational amplifier. The timing circuit further comprises a comparator circuit which includes (1) a voltage comparator, which compares the two voltages at its inputs, and can detect when the difference between its two inputs equals zero, the output of the comparator being connected to the gate of the MOSFET; (2) an isolation resistor connected between the output of the operational amplifier and one of the inputs of the voltage comparator; (3) a zener diode connected across the two inputs of the voltage comparator; and (4) a compensation resistor having one end connected to the other input of the voltage comparator, the other end of the resistor being grounded. The result being that, when the output of the amplifier reaches zero, the signal at the output lead of the comparator, and therefore at the gate of the MOSFET, causes the MOSFET to conduct, clamping the output of the operational amplifier at a zero voltage level, thus providing initialization of the timing cycle.

High-speed differential comparator circuitry with accurately adjustable threshold

Abstract: A high-speed differential comparator circuit is provided with an accurately adjustable threshold voltage. Differential reference voltage signals are provided to control the threshold voltage of the comparator. The common mode voltage of the reference signals preferably tracks the common mode voltage of the differential high-speed serial data signal being processed by the comparator circuit.