Topic
Comparator applications
About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.
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Papers
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27 Jun 2002TL;DR: In this paper, a comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively, and is enabled by a rising or a falling edge of the output that is coupled to a control means providing the second control signals.
Abstract: A comparator comprises a switching means for supplying two different threshold voltages to the comparator upon a first and a second control signal, respectively. The second control signal is enabled by a rising or a falling edge of the comparator output that is coupled to a control means providing the second control signal. The time interval that a varying input signal requires to change its amplitude crossing and in between the two threshold voltages can thus be detected by two subsequent rising or falling edges of the comparator output without the adverse influence of the comparator's meta-stability.
9 citations
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19 Dec 1983
TL;DR: In this article, a multiple input window comparator is proposed for use in apparatus requiring sensing of a voltage window, such as power supplies and system monitors, including a first comparator having multiple input transistors, each of which receives a signal to be compared.
Abstract: A multiple input window comparator for use in apparatus requiring sensing of a voltage window, such as power supplies and system monitors, including a first comparator having multiple input transistors, each of which receives a signal to be compared. The comparator characteristics for each input signal are balanced through the use of a current mirror circuit connected to each input transistor. A complementary second comparator circuit is provided which, in combination with the first comparator circuit, produces a signal indicating when one or more of the input signals exceeds the voltage boundaries (voltage window) defined by reference signals of the first and second comparator. The circuit topology of each of the first and second comparators produces a zero input voltage offset with respect to the respective reference voltage, such that the comparator output signal occurs substantially instantaneously and uniformly with the transition of the threshold voltage by one or more of the input signals. The comparator may be implemented with separate, discrete components or entirely on a single integrated circuit.
9 citations
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01 Mar 1982TL;DR: In this paper, a sensor-integrator utilizes a light sensing diode directly connected to the inputs of an operational amplifier, which forms part of a dual-slope integrator and directly integrates the current generated by the light-sensing diode thereby eliminating the need for preamplifiers and diode switching circuitry.
Abstract: A sensor-integrator utilizes a light sensing diode directly connected to the inputs of an operational amplifier. The operational amplifier forms part of a dual-slope integrator and directly integrates the current generated by the light sensing diode thereby eliminating the need for preamplifiers and diode switching circuitry.
9 citations
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03 May 1999TL;DR: In this article, the authors propose an adaptive delay stage (D) for delaying the data signal w.r.t. the clock signal, at least three bistable flip-flop stages (FF1-FF3), a first comparator stage (XOR1) connected to the outputs of the first and second Bistable stages, a second comparator Stage XOR2 connecting to the output of the second and third Stage YOR2, and a control stage (C) connected after the comparator stages.
Abstract: The arrangement has an adaptive delay stage (D) for delaying the data signal w.r.t. the clock signal, at least three bistable flip-flop stages (FF1-FF3), a first comparator stage (XOR1) connected to the outputs of the first and second bistable stages, a second comparator stage (XOR2) connected to the outputs of the second and third bistable stages and a control stage (C) connected after the comparator stages. The control stage evaluates the comparator output signals and controls the data signal delay. The first, second and third bistable stage data inputs are respectively the delayed data signal, the data signal delayed by a second delay element (T2) and the data signal delayed by a further second delay element (T2); their clock inputs all receive the clock signal.
9 citations
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01 Jan 2002TL;DR: For a given comparator circuit, the value of this resolution parameter changes depending upon the operating conditions and, hence, the comparator accuracy worsens as the temporal window allocated for comparison shrinks.
Abstract: parameter for proper detection.For a given comparator circuit, the value of this resolution parameter changesdepending upon the operating conditions. If the temporal window allocated forcomparison is long enough, takes an absolute minimum value which is inher-ent in the comparator device and which defines its maximum accuracy. As thetemporal w indow shrinks, the value of increases above its a bsolute minimumvalue and, hence, the comparator accuracy worsens. It highlights a trade-offbetween
9 citations