Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

On the design of quaternary comparators

Abstract: Quaternary logic requires a dedicated comparator circuit besides the usual add/sub unit which may not be optimal due to several reasons. In this paper, we have thoroughly discussed various alternative expressions for equality operator which serves as the basis for quaternary comparator. Then we have derived the necessary equations for single qudit comparator and extended it to serial multi qudit comparator. We have also shown the equations and design of single stage parallel comparator where restriction of fan-in is sacrificed for constant speed. We have ended our discussion with the design of a logarithmic stage parallel comparator which can compute the comparator output within log 2 (n) time delay for n qudits.

Low input impedance current comparator using in pulse-width modulation

Abstract: This work presents a design of continuous-time current comparator with ultra low input impedance, which especially benefits on enhancing the accuracy of pulse-width-modulation (PWM). The proposed design reduces the input impedance by utilizing common-gate structure as input stage. The further use of a common-source feedback structure also enables extremely reduction of the input impedance. In addition, the proposed design can be applied to perform precise comparison between two terminals with varied currents since the input impedances are well designed to be balanced. The experiment results demonstrate competitive performance. With input current of 25MHz square wave, the input impedance and propagation delay of comparator are merely 66.9Ω and 2.06ns respectively while the average power consumption is about 1.16mW under the implementation of TSMC 0.35µm CMOS process with 3V power supply.

High-speed latched comparator circuit with variable positive feedback

Abstract: A latched comparator circuit. The latched comparator circuit comprises a first and a second output terminal for outputting a first and a second output voltage, respectively, of the latched comparator circuit. Furthermore, the latched comparator circuit comprises a cross-coupled pair of transistors operatively connected between the first and the second output terminal for providing a positive feedback in the latched comparator circuit. In addition, the latched comparator circuit comprises a reset terminal for receiving a reset signal and reset circuitry arranged to balance the first and the second output voltage during a first phase of the reset signal and allow a voltage difference to develop between the first and the second output voltage during a second phase of the reset signal. Moreover, the latched comparator circuit comprises a load unit operatively connected to the cross-coupled pair of transistors and a bias circuit arranged to receive the reset signal and to bias the load unit such that a conductivity of the load unit is higher during the second phase of the reset signal than during the first phase of the reset signal, whereby said positive feedback is stronger during the second phase of the reset signal than during the first phase of the reset signal.

Precision Multi-Input Current Comparator and Its Application to Analog Median Filter Implementation

Abstract: In this work, a simple architecture of a precision CMOS multi-input current comparator is proposed. The circuit is based on the usage of a multi-input current Max circuit. The inherent “corner” error of the Max circuit is eliminated, using a feedback circuit, increasing thus the precision of the comparator. Only the digital output corresponding to the maximum (or minimum) input current is at logic 1, while the other outputs are at logic 0. An application of the comparator to the analog implementation of a current-mode median filter is also presented. A five-input comparator and a three-input median filter were fabricated using double-poly double-metal 2 μm CMOS MIETEC technology. Experimental results are given, to validate the theoretical analysis and to demonstrate the feasibility and the precision of the proposed circuits.

Low Input Resistance CMOS Current Comparator Based on the FVF for Low-Power Applications

Abstract: In this paper, a new low-voltage continuous-time current comparator is presented. The main idea is to use the flipped voltage follower as a key element for the comparator input stage. This configuration delivers a very low input resistance, which is mandatory for current-mode applications. Previous reported current comparators present a high-speed response; nevertheless, only few are suitable for low-voltage applications. Simulations and experimental results of a fabricated prototype using the complementary MOS 0.35- $\mu \text{m}$ technology are presented to demonstrate the circuit feasibility.