Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Electronic trip unit of a circuit breaker

Abstract: An electronic trip unit (20) which includes a processing unit (22) and a comparator circuit (24). The processing unit (22) receives an input voltage (VCC), and a reset signal (RESET) to reset the electronic trip unit (20), and generates a trip signal (TS) when sensed current of the electronic trip unit (20) exceeds a predetermined threshold. The comparator circuit (24) includes a first comparator (38) which receives the trip signal (TS) from the processing unit (22) and compares the trip signal (TS) with a predetermined reference voltage (VREF) determined based on the reset signal (RESET), and a second comparator (46) which compares a voltage generated by a power supply (11) with the predetermined reference voltage (VREF). The comparator circuit (24) determines whether the trip signal (TS) is for a valid trip event based comparison results of the first comparator (38) and the second comparator (46).

Analog-to-digital converter comparator circuit utilizing a reverse polarity sampling technique

Abstract: An analog-to-digital converter comparator circuit includes a pair of differential amplifiers having their outputs normally intercoupled in a subtractive sense. At a sampling strobe time, the output of one differential amplifier is reversed such that outputs of the two differential amplifiers are additive. The period of time during which the output signals add can be made as short as desired, for example by successively operating differential coupling circuits at the amplifier outputs through an intervening delay line. A very small aperture time is secured which is substantially shorter than the time constant of subsequent circuitry. A latch circuit receives the output of the comparator for assuming one of two different states in accordance with the comparator sampled output.

Pulse width modulation type digital to analog converter

Abstract: A DA converter has an N-bit binary counter which counts pulses of a predetermined frequency to generate a plurality of binary numbers within one conversion period. The binary counter supplies an output of lower n significant bits (n-1

High Speed Low Power CMOS Comparator for Pipeline ADCs

Abstract: This paper describes and analyzes a low power and high speed differential comparator. The designed comparator is intended to be implemented in a 10bit 20MHz pipeline analog-to-digital converter dedicated to RF WLAN applications. This comparator is based on the switched capacitor network using a two-phase nonoverlapping clock. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The analyses and simulation results which have been obtained using 0.8mum CMOS AMS process parameters, with a power supply voltage of 5V and an input common mode of 2-3V, show that this comparator exhibits a propagation delay of 17.3ns, a good accuracy and a low power consumption of about 0.8mW

A robust high-speed low input impedance cmos current comparator

Abstract: In this paper, a robust high-speed low input impedance CMOS current comparator is proposed. The front end of the comparator uses the modified Wilson current-mirror and diode-connected transistors to perform a current subtraction and current to voltage conversion simultaneously. The circuit is immune to the process variation and has low input impedances. HSPICE is used to verify the circuit performance with a 0.5 μm CMOS technology. The simulation results show the propagation delay of 1.67 ns, input impedances of 123 Ω, and 126 Ω, and average power dissipation of 0.63 mW for ± 0.1 μA input current under the supply voltage of 3 V.