Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

A 0.35 /spl mu/m CMOS comparator circuit for high-speed ADC applications

Abstract: A high-speed differential clocked comparator circuit is presented. The comparator consists of a preamplifier and a latch stage followed by a dynamic latch that operates as an output sampler. The output sampler circuit consists of a full transmission gate (TG) and two inverters. The use of this sampling stage results in a reduction in the power consumption of this high-speed comparator. Simulations show that charge injection of the TG adds constructively to the sampled signal value, therefore amplifying the sampled signal with a modest gain of 1.15. Combined with the high gain of the inverters, the sampled signals are amplified toward the rail voltages. This comparator is designed and fabricated in a 0.35 /spl mu/m standard digital CMOS technology. Measurement results show a sampling frequency of 1 GHz with 16 mV resolution for a 1 V input signal range and 2 mW power consumption from a 3.3 V supply. The architecture can be scaled down to smaller feature sizes and lower supply voltages.

On-chip power supply regulator and temperature control system

Abstract: An on-chip temperature control system includes a temperature sensor, which monitors a temperature of a chip, and a hysteresis comparator which checks whether the temperature is in an acceptable range. A reference adjustment circuit is responsive to the hysteresis comparator to adjust an on-chip voltage to control the temperature locally by adjusting a local supply voltage, if the temperature is out of range.

Dual threshold comparator circuit

Abstract: A dual threshold comparator circuit includes a comparator amplifier for comparing an analog input signal to a threshold waveform. The threshold waveform is generated in a circuit which includes positive and negative peak detector circuits and a slope detector circuit, all of which are connected to the analog signal source. A voltage divider is connected across the output of the positive and negative peak detector circuits. The threshold input to the comparator amplifier is connected to the common junction of first and second serially-connected impedances in the voltage divider. At the beginning of a particular half cycle of the analog input signal, the voltage across the voltage divider is equal to the difference of the most recent positive and negative peak voltages. The slope detector alters the effective impedances in the voltage divider to cause the threshold voltage to be equal to 25 or 75% of the total difference voltage, depending upon the slope of the analog signal.

Method and circuit for calibration of flash analog to digital converters

Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.

Comparator circuit with hysteresis

Abstract: A comparator with hysteresis which has a bias current circuit, a differential input stage, and an output stage is disclosed. The differential input stage uses a parallel transistor and an enabling transistor connected in parallel to one of the differential pair transistors to create hysteresis. The parallel transistor and enabling transistor are used to generated an effective offset voltage which must be overcome for the comparator to switch states.