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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


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Patent
Hyun Jong Shin1, Peter Hong Xiao1
18 Jan 1996
TL;DR: In this article, a self-biased, fully differential, complementary receiver is presented, which includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage.
Abstract: A self-biased, fully differential, complementary receiver apparatus and method is presented. The receiver accepts differential inputs that can vary over the full rail-to-rail common mode voltage range. It produces double-ended complementary outputs swinging rail-to-rail useful in signal level conversion and comparator applications. The receiver includes a dual, fully complementary and mirror-symmetrical arrangement of a differential input stage, a biasing stage and an output stage. A self biasing voltage is generated with a balanced voltage divider coupled between the outputs of the biasing stages. This frees both biasing outputs for use as analogous but complementary receiver outputs while providing the receiver with all the advantages of self bias. For small signal differential inputs, the input and biasing stages operate in their linear region useful for amplifier applications. Whereas the circuit is most advantageously implemented using both p-type and n-type CMOS transistors, it can similarly be advantageously implemented with bipolar transistors. Alternate circuit configurations are described.

36 citations

Patent
08 May 1995
TL;DR: In this paper, a fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance, which triggers a disabling circuit of the output power transistor for a preset period of time when the current level through the output stage uncontrollably rises beyond a threshold.
Abstract: A fully digital, current mode, PWM control is realized by employing two distinct comparators, both reading the voltage drop on a sensing resistance. The first comparator exerts an open-loop current mode control. The second comparator, establishing a second higher current threshold than the current threshold set by the first comparator, triggers a disabling circuit of the output power transistor for a preset period of time, when the current level through the output stage uncontrollably rises beyond the second threshold. This may occur because of an insufficient discharge from the load circuit inductance during off-phases of the output power transistor of the extra energy stored during switching delay periods of the first (open loop control) comparator. The frequency of the sequence of bursts may be precisely controlled to be well outside the frequency range of interest to prevent disturbances.

36 citations

Patent
12 Jul 1973
TL;DR: In this article, a battery charger is equipped with a current adjusting device, which continuously measures the current output from the charger and feeds the readings to a current comparator, and the terminal voltage of the battery is also continuously read and fed to a voltage comparator.
Abstract: A battery charger is equipped with a current adjusting device. A current sensor continuously measures the current output from the charger and feeds the readings to a current comparator. The terminal voltage of the battery is also continuously read and the readings are fed to a voltage comparator. A voltage reference feeds a constant reference voltage to the voltage comparator. The voltage comparator compares the battery voltage with the reference voltage and feeds a signal dependent upon the voltage difference and in accordance with a preselected program to a current reference. The current reference delivers a signal dependent on the output of the voltage comparator and in accordance with a preselected program to the current comparator. The current comparator to the the signal received from the current sensor tothe signal received from the current reference and provides an output signal to cause the current adjusting device to adjust the charging current to the values called for by the preselected program. A typical charge program which can be selected is a first charging mode at the initial charge rate of the battery until the battery voltage rises to a preselected value slightly below the gassing voltage. This is followed by a second charging mode wherein the charging current is gradually diminished so as to hold the voltage constant at the preselected value. When the charging current drops down to the finishing rate of the battery, a third mode commences wherein the current is held at the finishing rate regardless of further increase of the battery voltage. The charge can be terminated by a timing device set for total charge time or alternately for a predetermined charge period at the finishing rate.

35 citations

Patent
Hisao Katoh1
27 Oct 1999
TL;DR: In this paper, a phase comparator circuit was proposed to reduce the effects of offset and jitter, and a data phase-locked loop circuit incorporating the phase comparators was constructed.
Abstract: A phase comparator circuit reducing the effects of offset and jitter, and a data Phase Locked Loop circuit incorporating the phase comparator circuit. The phase comparator circuit includes a Delay Locked Loop circuit for outputting a delay, signal PLDTD with a delay according to an oscillation frequency of a voltage controlled oscillator, with respect to an input data PLDT, a D-type flip-flop for outputting a delay signal PLDTL by latching an input data PLCK according to an oscillation clock PLCK output from a voltage controlled oscillator, and a phase comparator for comparing phases of delay signals PLDTD and PLDTL.

35 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100