Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

A 10-bit 5-Msample/s CMOS two-step flash ADC

Abstract: A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

A 100-MHz pipelined CMOS comparator

Abstract: The authors describe the design of a VLSI-compatible CMOS comparator for high-speed applications. An examination of various generic approaches to obtaining the nonlinear amplification needed to perform the function of comparison leads to the conclusion that this amplification can best be obtained by means of regeneration. Based on this conclusion, a CMOS comparator has been designed wherein voltage comparisons are accomplished directly by a pipelined cascade of two regenerative sense amplifiers, without the use of a preamplifier. To ensure an input resolution of at least 8-bits, offset cancellation is incorporated in the first sense amplifier. The comparator has been integrated in a 2- mu m CMOS technology and has a maximum sampling rate of over 100 MHz; it operates from a single +5-V supply and dissipates only 3.6 mW at its maximum sampling rate. >

An Energy-Efficient 15-Bit Capacitive-Sensor Interface Based on Period Modulation

Abstract: This paper presents an energy-efficient capacitive-sensor interface with a period-modulated output signal. This interface converts the sensor capacitance to a time interval, which can be easily digitized by a simple digital counter. It is based on a relaxation oscillator consisting of an integrator and a comparator. To enable the use of a current-efficient telescopic OTA in the integrator, negative feedback loops are applied to limit the integrator's output swing. To obtain an accurate ratiometric output signal, auto-calibration is applied. This eliminates errors due to comparator delay, thus enabling the use of a low-power comparator. Based on an analysis of the stability of the negative feedback loops, it is shown how the current consumption of the interface can be traded for its ability to handle parasitic capacitors. A prototype fabricated in 0.35 μm standard CMOS technology can handle parasitic capacitors up to five times larger than the sensor capacitance. Experimental results show that it achieves 15-bit resolution and 12-bit linearity within a measurement time of 7.6 ms for sensor capacitances up to 6.8 pF, while consuming only 64 μA from a 3.3 V power supply. Compared to prior work with similar performance, this represents a significant improvement in energy efficiency.

Realizing analog-to-digital converter on a digital programmable integrated circuit

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

Synchronization of multiphase synthetic ripple voltage regulator

Abstract: A multiphase synthetic ripple voltage generator for a multiphase DC-DC regulator including a master clock circuit that generates a master clock signal, sequence logic and a ripple regulator for each phase. The DC-DC regulator includes multiple switching circuits, each responsive to a corresponding PWM signal to switch input voltages via a phase node through an output inductor to develop an output voltage. The sequence logic sets each PWM signal in sequential order based on the master clock signal. Each ripple generator includes a transconductance amplifier, a ripple capacitor and a comparator. The transconductance amplifier has an input coupled to a corresponding output inductor and an output coupled to a corresponding ripple capacitor. The comparator has a first input coupled to the ripple capacitor, a second input receiving an error voltage, and an output coupled to the sequence logic for resetting a corresponding PWM signal.