Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process

Abstract: This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.

Capacitive level sensing device

Abstract: A capacitance sensing circuit utilizes an operational amplifier connected in a comparator configuration. The capacitance to be measured is connected to one input of the operational amplifier and is also connected to the output of the operational amplifier through a resistor to form a free-running multivibrator. The period of the multivibrator output depends upon the value of capacitance being measured. A switching transistor is connected to the output of the operational amplifier to cause a changing current output signal. The output signal is obtained as a change of current in a current sensor connected to the collector of the transistor.

Phase and frequency comparator circuit for phase locked loop

Abstract: A phase and frequency detector circuit includes both a phase comparator such as an exclusive-OR gate possessing high phase sensitivity, and a frequency-phase comparator that is sensitive to differences in frequency. The outputs of these circuits are combined to provide a single output signal offering both frequency discrimination and sharp phase discrimination.

Comparator having temperature and process compensated hysteresis characteristic

Abstract: A MOS hysteresis comparator having a source transistor bias circuit which generates a source current Is that compensates for temperature and manufacturing process variations, thereby providing a hysteresis characteristic which is substantially insensitive to such temperature and manufacturing process variations. The source transistor bias circuit includes a set of MOS transistors which replicate the comparator load currents which occur at the switch points of the comparator, and a source transistor which mirrors the sum of the replicated currents to form the source current Is of the comparator.

Analysis and Background Self-Calibration of Comparator Offset in Loop-Unrolled SAR ADCs

Abstract: In conventional charge redistribution successive approximation register (SAR) ADCs that use a single comparator, the comparator offset causes no distortion but a dc shift in the transfer curve. In loop-unrolled (LU) SAR ADCs, on the other hand, mismatched comparator offset voltages introduce input-level-dependent errors to the conversion result, which deteriorates the linearity and limits the resolution. Still, the literature lacks a quantitative analysis on this phenomenon, and the resolution of most reported SAR ADCs of this kind, until recently, has been limited to 6 bit. In this paper, we analyze the effects of comparator offset voltage mismatch in LU-SAR ADCs, and establish the quantitative relation between individual offsets and the signal-to-noise-and-distortion ratio (SNDR) and the effective-number-of-bits. A statistical linearity model is proposed for yield estimation. Finally, an on-line deterministic calibration technique for auto-zeroing dynamic comparator offset is presented to treat the offsets mismatch and improve linearity. A 150-MS/s 8-bit LU-SAR ADC is fabricated in a 130-nm CMOS technology to validate the concept. The measured result shows that the calibration improves the SNDR from 33.7 to 42.9 dB. The ADC consumes $640~\mu \text{W}$ from a 1.2-V supply with a figure-of-merit of 37.5 fJ/conv-step.