scispace - formally typeset
Search or ask a question
Topic

Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


Papers
More filters
Proceedings ArticleDOI
28 May 2000
TL;DR: A high-speed low current comparator with low input impedance using a simple biasing method using 0.35 /spl mu/m CMOS technology is proposed and results demonstrate the propagation delay is about 2.8 nsec and the average power consumption is 0.58 mW.
Abstract: A high-speed low current comparator with low input impedance using a simple biasing method is proposed. Simulation results demonstrate the propagation delay is about 2.8 nsec and the average power consumption is 0.58 mW for 0.1 /spl mu/A input current at supply voltage of 3 V using 0.35 /spl mu/m CMOS technology.

29 citations

Journal ArticleDOI
TL;DR: In this paper, a discussion of the phase-controlled loop with a sawtooth comparator is presented, where the main emphasis is on finding the pull-in range of the loop.
Abstract: Because of the recent interest in phase-controlled oscillators, a discussion of the phase-controlled loop with a sawtooth comparator is presented. The main emphasis is on finding the pull-in range of the loop. A companion paper in this issue (Ref. 4) deals with applications and shows how design parameters can be obtained from results developed here.

29 citations

Journal ArticleDOI
TL;DR: In this article, the authors proposed a continuous-time CMOS current comparator, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters.
Abstract: Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 mm CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.

29 citations

Proceedings ArticleDOI
03 Aug 2010
TL;DR: This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator based on a novel parallel-prefix algorithm which drastically reduces the switching activity of the internal nodes of the circuit.
Abstract: This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is based on a novel parallel-prefix algorithm which drastically reduces the switching activity of the internal nodes of the circuit. When implemented by using the ST 90nm-1V technology, the proposed 64-bit comparator exhibits an energy dissipation of only 0.77μW/MHz and a delay of 258ps. With respect to a recently published low-power high-speed parallel-prefix adder, the proposed design shows an energy dissipation reduction of 23% and a speed improvement of 7%.

29 citations

Patent
26 Feb 2009
TL;DR: An analog-to-digital converter that converts an analog input signal into a digital signal includes a comparator configured to compare a reference signal with an input signal and, if the input signal matches the reference signal, inverts an output.
Abstract: An analog-to-digital converter that converts an analog input signal into a digital signal includes a comparator configured to compare a reference signal with an input signal and, if the input signal matches the reference signal, inverts an output; a counter configured to count a comparison time of the comparator; a control circuit configured to monitor the output of the comparator; a voltage generating circuit configured to generate, if a monitoring result obtained by the control circuit indicates that the output of the comparator is at a predetermined level, a direct current voltage in accordance with the monitoring result; and an analog adder configured to add the voltage generated by the voltage generating circuit to the input signal and supply a sum signal to an input terminal of the comparator.

29 citations


Network Information
Related Topics (5)
CMOS
81.3K papers, 1.1M citations
84% related
Electronic circuit
114.2K papers, 971.5K citations
83% related
Capacitor
166.6K papers, 1.4M citations
82% related
Integrated circuit
82.7K papers, 1M citations
81% related
Amplifier
163.9K papers, 1.3M citations
81% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100