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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


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Patent
05 Sep 1980
TL;DR: In this paper, a threshold comparator with feedback is used to determine the negative zero-crossing transition of the input signal on condition that the previous half-cycle has exceeded the positive reference threshold.
Abstract: In carrier and timing recovery systems for high performance data modems it is essential to employ threshold comparators and to be able to determine accurately zero-crossing instants. The circuit of the invention comprises a comparator with feedback which produces a positive transition of the comparator output in response to the negative zero-crossing transition of the input signal on condition that the previous half-cycle of the input signal has exceeded the positive reference threshold. In a practical arrangement two comparators (C1, C2) provided together with a pair of bistable storage elements (D1,D2) which produces a narrow pulse in response to the negative zero-crossing transition of an input signal (IPS) provided that the input signal (IPS) has exceeded the positive reference threshold (+VT) applied to the second comparator (C2).

27 citations

Proceedings ArticleDOI
07 Feb 2017
TL;DR: In this article, a swing-boosted differential scheme was proposed to reduce the effect of comparator noise by boosting the signal slope at the comparator input, demonstrating an FOM of over 160dBc/Hz.
Abstract: With the emergence of wearable and implantable technologies, there has been growing demand on development of key enabling circuits for ultra-low-power sensor interface SoCs. As a reference-frequency generation block for clock management of the overall system, the relaxation oscillator has been widely adopted since it can provide a controllable and well-defined untrimmed frequency with low-cost circuits. In the past decade, the major goal in the design of the relaxation oscillators has been the improvement of phase-noise figure-of-merit (FOM) closer to the fundamental limit of 169dBc/Hz [1]. There have been feedback approaches to internally generate reference voltages for comparison, hence compensating the comparator circuit delay [2–4]. Since the delay compensation relies on the feedback operation, power consumption by analog circuits to meet the required bandwidth of the feedback loop eventually limits FOM. Recently, a swing-boosted differential scheme was proposed to reduce the effect of comparator noise by boosting the signal slope at the comparator input, demonstrating an FOM of over 160dBc/Hz [5]. However, the boosted voltage swing can increase stress on the input transistors of the comparator. In addition, a high-speed comparator is also needed to reduce the effect of the circuit delay on the output frequency. While most of previous works achieved good FOMs with MHz oscillators, implementation of low-frequency relaxation oscillators presents additional challenges since it requires excessive area for RC and power consumption by analog circuits with leakage not scaled down along with the output frequency.

27 citations

Patent
Teruo Sasaki1
12 Sep 1997
TL;DR: In this article, a multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator and a reception electric field strength detector, and a reference voltage generating circuit.
Abstract: A multivalued FSK demodulation window comparator includes an MSB comparator, an LSB comparator, a reception electric field strength detector, and a reference voltage generating circuit. The MSB comparator determines at least the polarity of a frequency shift of a radio frequency. The LSB comparator determines the absolute value of the frequency shift of the radio frequency. The reception electric field strength detector detects the strength of a radio signal and outputs a signal corresponding to the detected strength. The reference voltage generating circuit changes the reference voltages of the LSB comparator in accordance with an output voltage from the reception electric field strength detector. When the output voltage from the reception electric field strength detector is not higher than a predetermined level, a reference voltage from the reference voltage generating circuit changes.

27 citations

Patent
05 Oct 2009
TL;DR: In this paper, a self-calibration frequency synthesizer for implementing a self calibrration method includes a first phase lock loop consisting of a reference oscillator, a phase comparator and a first charge pump.
Abstract: The frequency synthesizer for implementing a self-calibration method includes (i) a first phase lock loop comprising: a reference oscillator, a phase comparator, a first charge pump, a first loop filter, a voltage controlled oscillator, and a multimode divider counter controlled by a modulator and connected to the phase comparator; (ii) a high frequency access comprising a digital-analogue converter connected to an input of the voltage-controlled oscillator; (iii) a second charge pump connected to the phase comparator; and (iv) a second loop filter in the high frequency access. The second charge pump forms, when switched on, a second phase lock loop with the second loop filter. To calibrate gains of the converter, a voltage comparator compares an output voltage of the converter with a voltage stored in the second loop filter, after disconnecting the second charge pump from the second phase lock loop, previously locked onto a determined output frequency.

27 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: In this paper, the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed has been discussed, which combines the good features of the resistive dividing comparator and the differential current sensing comparator.
Abstract: This paper discusses the design and analysis of a latching comparator using charge sharing circuit topology for low power and high speed. This topology combines the good features of the resistive dividing comparator and the differential current sensing comparator. This design will be focusing on the minimization of propagation delay and the power dissipation of the comparator, which will improves the comparator performance. Simulation results have been obtained using 0.18μm technology, for a 100 MHz clocked comparator, considering 1.8V supply voltage and 1.8V input range. Design has been carried out in SILVACO EDA tool, the schematic simulations are using Gateway SILVACO EDA tool and layout simulations are verified using Expert SILVACO EDA tool.

27 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100