Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Signal averaging for optical time domain relectometers

Abstract: Means for digitizing and averaging the signals in an optical time domain reflectometer are disclosed in which a comparator is used to output a 1 or 0 into an arbitrarily large number of successive time-bins. In each comparator choice, the analog voltage signal from the OTDR receiver is compared to a selected analog voltage value. The selected value is chosen randomly from the range of available signals in the interval of interest; and each such valve is used to provide a comparator input into every time-bin during one waveform recovery. Each comparator output signal (1 or 0) is directed to a separate time-bin (counter), representing the desired time interval (resolution). Subsequent comparator output signals are added to each time bin. The waveform recovery runs are repeated until an acceptable signal-to-noise result is achieved. Each waveform run uses a different voltage for comparison to the receiver voltage. Such comparison voltages may be selected by a random generator; or an ordered series of comparison voltages may be used.

A 13b SAR ADC with Eye-opening VCO Based Comparator

Abstract: A low-power and high accuracy comparator based on voltage controlled ring-oscillator (VCO) is presented. By using the dead zone of phase detector effectively, the VCO comparator automatically changes its noise level depending on the input voltage level (Δvin). When Δvin is large, the comparator operates as a low-power delay-line based comparator. On the other hand, when Δvin is small, the VCO is enabled and eye is opened during the oscillation. This suppress input referred noise and enables accurate conversion. The number of oscillation cycle for one comparison is inversely proportional to Δvin and adaptive noise reduction is realized. The VCO comparator does not require any sort of tuning. A 13b SAR ADC with proposed VCO based comparator was fabricated in 65-nm CMOS. By off-chip LMS calibration, the ADC achieves SNDR 66 dB at 1 MS/s with FoM of 29fJ/conv.step. I. INTRODUCTION Towards the “trillion sensor universe”, the number of sensors around us will keep on increasing. To sense environmental information (e.g. temperature, humidity, gas, etc.), high precision ADCs are required. Even though a number of low-power SAR ADCs for sensor nodes have been presented, most of their target SNDR is lower than 60 dB [1,2]. This is because reducing kT/C noise, C-DAC mismatch, and comparator noise with small power dissipation is very

Low-power substrate bias generator disabled by comparators for supply over-voltage protection and bias target voltage

Abstract: A substrate bias generator has a ring oscillator disabled when a supply over-voltage condition is detected by a supply comparator, or when a target substrate voltage is reached. A substrate comparator compares the substrate voltage to a reference generated by a p-channel sense transistor that is independent of the substrate voltage. The substrate is sensed by an n-channel sense transistor with only its bulk connected to the substrate voltage. Current sources for the sense transistors and comparator are controlled by bias voltages generated by a voltage divider that switches from a high-power state to a low-power state once the substrate target is reached. Feedback turns off a high-current resistor, limiting current to that passing through a low-current resistor. The bias voltages are adjusted to reduce current to the sense transistors and comparator, reducing power. High current and power are used for fast sensing before the substrate target is reached.

A clock generator and phase comparator for use in such a clock generator

Abstract: 1. A clock generator contains a reference oscillator (10), a digital closed delay chain (12), a digital frequency divider (14) and a digital phase comparator (16). The frequency divider (14) is connected between the output of the adjustable delay chain (12) and one input of the phase comparator (16). The output of the reference oscillator (10) is connected to a further input of the phase comparator (16). Between the output of the phase comparator (16) and the delay chain (12) a digital up-down counter (18) is connected, the counting direction of which is determined by the output signal of the phase comparator (16) and by means of which the corresponding length of the delay chain (12) is adjustable.