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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


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Patent
14 Dec 1994
TL;DR: In this paper, a switch voltage is presented to both an inverting input of a first comparator and a non-inverting input of the second comparator, and the switch output voltage is compared to the reference voltages on the two comparators.
Abstract: Electronic circuitry is disclosed for interfacing with a plurality of two-position switches to determine if each switch is opened, closed or faulty to some extent. Each switch is connectable in series with a pull-up resistor and between two different voltage values. The switch provides an output voltage at the connection of one terminal of the switch with the pull-up resistor. This switch voltage is presented to both an inverting input of a first comparator and a non-inverting input of a second comparator. The non-inverting input of the first comparator has a reference voltage of a certain value applied thereto, while the inverting input of the second comparator has a reference voltage of a certain value also applied thereto, the reference voltage values being different so as to define a "window" or "dead band" region of voltage. The switch output voltage is compared to the reference voltages on the two comparators. If the switch is closed, the comparator outputs will assume certain states. On the other hand, if the switch is opened, the comparator outputs will assume the opposite states. Finally, if the switch is faulty such that a finite impedance value is developed across the terminals of the switch, the voltage value will then be generated which causes both comparator outputs to assume the same state, thereby indicating a faulty switch to subsequent signal processing circuitry.

24 citations

Patent
27 Jun 1984
TL;DR: In this paper, a control circuit for an electric arc welder is responsive to the operation of a torch or a gun mounted control switch, and the control relay can be deenergized either by the welder operating the control switch a second time or by extinguishing the arc, such as by removing the torch from the workpiece; either will disable the latch circuit and terminate the welding operation.
Abstract: A control circuit for an electric arc welder is responsive to the operation of a torch or gun mounted control switch. A first comparator has one input connected to the gun switch and the other input to a reference voltage source. When the gun switch is closed, the output of the comparator will cause a control relay to be energized. When a welding arc is established, a reed switch closes and provides an input to a second comparator which effectively provides a latch to hold the control relay energized. After a predetermined time delay, typically in the order of 1 second, a timer circuit will provide an output to one input of a third comparator, the other input of which is connected to the gun switch. A subsequent closure of the gun switch will caused the output of the third comparator to change the level of the reference voltage, changing the outputs of the first two comparators, thereby removing the latch and deenergizing the control relay. Thus, the control relay can be deenergized either by the welder operating the control switch a second time or by extinguishing the arc, such as by removing the torch from the workpiece; either will disable the latch circuit and terminate the welding operation.

24 citations

Proceedings ArticleDOI
01 Nov 2014
TL;DR: This paper presents the design of a modified StrongArm regenerative comparator in 0.13-μm CMOS technology, operating at a supply voltage of 200-mV, using a pair of cross-coupled P-type transistors to replace the conventional cross- coupled inverters, improving the comparison time and voltage headroom.
Abstract: This paper presents the design of a modified StrongArm regenerative comparator in 0.13-μm CMOS technology, operating at a supply voltage of 200-mV. The comparator uses a pair of cross-coupled P-type transistors to replace the conventional cross-coupled inverters, improving the comparison time and voltage headroom. A robust S-R latch is proposed to solve the race condition which occurs when the S-R latch enters a forbidden state especially during ultra-low supply voltage operation. As a result, the circuit shows up to 1.8× voltage offset reduction and 73% less sensitivity in the delay per input voltage difference (delay/log(ΔV IN )), which is about 65ns/decade, compared to conventional latched comparators.

24 citations

Journal ArticleDOI
TL;DR: A new fast low-power single-clock-cycle binary comparator is presented, which high speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes.
Abstract: A new fast low-power single-clock-cycle binary comparator is presented. High speed is assured by using parallel-prefix architecture, whereas low power is guaranteed by reducing the switching activities of the internal nodes. When implemented with the ST 90 nm 1 V CMOS technology, the proposed circuit exhibits a 4.5 GHz maximum running frequency and 0.77µW/ MHz energy dissipation. Copyright © 2010 John Wiley & Sons, Ltd.

24 citations

Patent
24 Oct 2012
TL;DR: In this article, a hysteretic comparator is used to provide a feedback signal providing a representation of the output voltage of the switched mode power supply and a second input of the comparator to receive a reference voltage.
Abstract: A hysteretic power converter constituted of: a switched mode power supply; a hysteretic comparator, a first input of the comparator arranged to receive a feedback signal providing a representation of the output voltage of the switched mode power supply and a second input of the comparator arranged to receive a reference voltage; a ramp capacitor coupled to one of the first and second input of the comparator; a current source, a terminal of the current source coupled to the ramp capacitor and arranged to drive current to the ramp capacitor; and a switchable current source, a terminal of the switchable current source coupled to the ramp capacitor, the switchable current source arranged to drive current to the ramp capacitor in a direction opposite the current driven by the current source, wherein the switchable current source is alternately enabled and disabled responsive to the output of the hysteretic comparator.

24 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100