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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


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Patent
Changku Hwang1
18 Dec 2000
TL;DR: In this article, a negative voltage generator for an integrated circuit includes a charge pump responsive to the current loading on its output terminal, which is connected to a comparator which compares the output node of the charge pump with a reference potential.
Abstract: A negative voltage generator for an integrated circuit includes a charge pump responsive to the current loading on its output terminal. The charge pump is connected to a comparator which compares the output node of the charge pump with a reference potential. The comparator provides an analog output signal to a variable frequency oscillator, which in turn controls the charge pump. Variations in current loading caused the comparator to make appropriate changes in the oscillation frequency.

20 citations

Patent
Xiaotang Lu1
27 Feb 2004
TL;DR: In this article, a system and a method for testing a comparator include generating two triangular waveform segments having the same period and different amplitudes, inputting the two triangularwaveform segments into the comparator, receiving an output of the comparators, and calculating threshold voltages based on the output.
Abstract: A system and a method for testing a comparator include generating two triangular waveform segments having the same period and different amplitudes, inputting the two triangular waveform segments into a comparator, receiving an output of the comparator, and calculating threshold voltages of the comparator based on the output. A periodic waveform can also be generated with repeating triangular waveform segments having the same period and different amplitudes as input to the comparator.

20 citations

Patent
24 Nov 1999
TL;DR: In this article, a hiccup mode current protection circuit for switched mode power converters for high power applications is presented, which features a comparator for comparing an indicating voltage to a reference voltage and outputting a control signal to a disabling input where the indicating voltage exceeds a predetermined voltage threshold.
Abstract: A hiccup mode current protection circuit for switched mode power converters for high power applications is provided. The circuit features a comparator for comparing an indicating voltage to a reference voltage and outputting a control signal to a disabling input where the indicating voltage exceeds a predetermined voltage threshold. The control signal also causes a switch to reduce the reference voltage to ensure that the comparator continues to output the control signal regardless of a drop in the indicating voltage. The control signal is maintained by a comparator for only a predetermined time period such that the switch eventually returns the reference voltage to its pre-reduction state, allowing the comparator to discontinue outputting the control signal if the indicating voltage is below the predetermined voltage threshold.

20 citations

Patent
22 Nov 1999
TL;DR: A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a three-input logic NOR gates as discussed by the authors, which has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank.
Abstract: A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

20 citations

Proceedings ArticleDOI
G.A. Al-Rawi1
07 Aug 2002
TL;DR: A new technique that uses a differential amplifier in closed-loop negative feedback configuration to measure the offset of a dynamic latch can then be stored and canceled using standard techniques, thus allowing gain reduction in the preamplifier stages in high-resolution comparators.
Abstract: This paper introduces a new technique that uses a differential amplifier in closed-loop negative feedback configuration to measure the offset of a dynamic latch. This offset can then be stored and canceled using standard techniques, thus allowing gain reduction in the preamplifier stages in high-resolution comparators. A CMOS comparator was designed based on the proposed technique. The output of the comparator drives a 1 pF load capacitance and is held valid for at least 75% of the cycle. The performance of the comparator was simulated using HSPICE with the worst-case combination of differences as large as 10 mV between the thresholds of nominally identical transistors, where it achieved an offset of 400 /spl mu/V at a 40 MHz clock rate in 0.6 /spl mu/m CMOS technology while dissipating 1 mW from a 3.3 V power supply.

20 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100