Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

A new rail-to-rail ultra low voltage high speed comparator

Abstract: This paper presents a new rail-to-rail input highperformance regenerative comparator suitable for low-voltage low-power applications, e.g. bio-implantable circuits. In this circuit the body of the PMOS transistor is used as comparator's input. A technique is proposed to increase the speed of the circuit. The proposed comparator has a good performance in weak inversion (sub-threshold). Simulations are done in the 0.18-μm CMOS technology with a supply voltage of 0.5 V. The propagation delay time of the second proposed comparator is 16.4 ns, the power dissipation is 20 nW and the power delay product is 0.33 fJ in clock frequency of 5 MHz and input voltage of 500 μV. Also the supply voltage can be decreased to 0.3 V.

A High-Speed High-Resolution Latch Comparator for Pipeline Analog-to-Digital Converters

Abstract: A high-speed and high-resolution comparator intended to be implemented in a 12 bit 100 MHz pipeline analog-to-digital converter (ADC) for frequency wireless local area network application is proposed. The designed comparator presents a rail-to-rail input range preamplifier without any capacitance required. This comparator with a novel architecture of output stage achieves very high speed at a low kickback noise. The simulation results using a 0.35 mum TSMC CMOS process technology show that this comparator exhibits a propagation delay of 2.8 ns and has a very high resolution for a rail-to-rail input signal range, while consumes only 1.0 mW of power with 5.0 V voltage supply.

Schmitt Trigger with Controllable Hysteresis Using Current Conveyors

Abstract: Active elements working in the current or mixed mode are still attractive for the design of analog functional blocks. The current conveyor (CC) was defined already in 1968. This paper deals with hysteresis comparators using second generation current conveyor. The comparator is basically a pulse circuit. In these circuits, the maximum rate of change in the output voltage is required during switching from one state to another. In comparators with operational amplifiers the switching time is given by the slew rate of the operational amplifier used, which is not too high. If a current conveyor is used, the time of switching the comparator gets shorter. The comparator is capable to operate at a higher frequency bands and if it is used, for example, in converters, a higher operating frequency can be reached. The connection of an inverting and a non-inverting comparator with adjustable hysteresis is shown as a practical implementation. Using the AD844, results of experimental measurements are presented that confirm the theoretical assumptions and the results of computer simulation.

A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping

Abstract: The linearity of a stochastic flash analog-to-digital converter (ADC) with two groups of comparators is improved by reference swapping. If the input offset of a comparator is larger than the linear input range of its comparator group, the reference voltage of the comparator is swapped with the reference voltage of the other comparator group. The reference swapping doubles the number of comparators providing a meaningful result in determining the ADC output. A stochastic flash ADC linearized by the reference swapping has been implemented in a 65-nm CMOS process. The peak signal-to-noise + distortion ratio is 39 dB, which is 3-dB higher than that without the reference swapping.

High accuracy MOS comparator

Abstract: The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to a FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.