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Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.


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Patent
09 Oct 1980
TL;DR: In this article, a thermal printhead has a temperature sensing diode whose output is applied, as a reference voltage, to the other input of the comparator, clearing the latch.
Abstract: An electronic thermal printer has a thermal printhead to which is applied a train of pulses which is pulse width modulated. A power switch connects and disconnects the printhead from a DC power source. The pulse train is integrated, scaled and applied as an input to a comparator circuit. The thermal printhead has a temperature sensing diode whose output is applied, as a reference voltage, to the other input of the comparator. During a print cycle, the output of the temperature sensing diode is cut off and the reference voltage is capacitively stored and held as the reference voltage. The output of the comparator circuit clears a latch circuit whose input is provided by a system clock and whose output is connected to control the power switch. The comparator provides an output when the integrated voltage reaches the reference voltage, clearing the latch. Since the latch is supplied with signals from the system clock, a constant frequency is maintained. However, the varying output from the comparator clearing the latch provides varying pulse widths. In this manner, pulse width modulation of the voltage input pulses to the thermal printhead is achieved.

70 citations

Journal ArticleDOI
TL;DR: In this paper, a dynamic latched comparator with offset voltage compensation is presented, which uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage.
Abstract: A novel dynamic latched comparator with offset voltage compensation is presented. The proposed comparator uses one phase clock signal for its operation and can drive a larger capacitive load with complementary version of the regenerative output latch stage. As it provides a larger voltage gain up to 22 V/V to the regenerative latch, the input-referred offset voltage of the latch is reduced and metastability is improved. The proposed comparator is designed using 90 nm PTM technology and 1 V power supply voltage. It demonstrates up to 24.6% less offset voltage and 30.0% less sensitivity of delay to decreasing input voltage difference (17 ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption. In addition, with a digitally controlled capacitive offset calibration technique, the offset voltage of the proposed comparator is further reduced from 6.03 to 1.10 mV at 1-sigma at the operating clock frequency of 3 GHz, and it consumes 54 μW/GHz after calibration.

68 citations

Journal ArticleDOI
TL;DR: This paper describes a very simple CMOS Schmitt trigger circuit, well suited for low-voltage and high-speed applications, and allows the construction of a very compact window comparator.
Abstract: Gates with input hysteresis are often necessary in circuits operating in noisy environments. Described is a very simple CMOS Schmitt trigger circuit, well suited for low-voltage and high-speed applications. The circuit also allows the construction of a very compact window comparator.

67 citations

Journal ArticleDOI
TL;DR: Property of the phase-controlled oscillator with a sawtooth comparator that have been mentioned in the literature for sinusoidal comparators are analyzed and there is new theoretical material on the effect of fast jitter and noise.
Abstract: A sawtooth phase comparator has advantages over the more common sinusoidal comparator in a phase-controlled oscillator because its output is linear for larger values of phase error. For some applications, it is no more complex or expensive than the sinusoidal comparator. This paper analyzes properties of the phase-controlled oscillator with a sawtooth comparator that have been mentioned in the literature for sinusoidal comparators. In addition, there is new theoretical material on the effect of fast jitter and noise. The properties of the circuit are presented in a manner which is convenient for design. Since it is easier to analyze the circuit with a sawtooth comparator, many applications of the device have been considered. Because of this wide viewpoint, the paper may be helpful in understanding the phase-controlled oscillator in general.

67 citations

Proceedings ArticleDOI
01 Nov 2010
TL;DR: In this paper, the authors present a design for an on-chip high-speed clocked-comparator for high frequency signal digitization, which is implemented in 65nm CMOS technology.
Abstract: This paper presents a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. Also, the paper presents a new cost effective technique for measuring the maximum speed of the clocked comparator. The measurement and simulation results show that the proposed design has an average of 31% higher speed and ∼17% less active area than the conventional design.

67 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202319
202269
20185
201747
201687
2015100