Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

A CMOS low-power low-offset and high-speed fully dynamic latched comparator

Abstract: This paper presents a novel dynamic latched comparator that demonstrates lower offset voltage and higher load drivability than the conventional dynamic latched comparators. With two additional inverters inserted between the input- and output-stage of the conventional double-tail dynamic comparator, the gain preceding the regenerative latch stage is improved. The complementary version of the regenerative latch stage, which provides larger output drive current than the conventional one at a limited area, is implemented. The proposed circuit is designed using 90nm CMOS technology and 1V power supply voltage, and it demonstrates up to 19% less offset voltage and 62% less sensitivity of the delay to the input voltage difference (17ps/decade) than the conventional double-tail latched comparator at approximately the same area and power consumption.

High-speed low-power common-mode insensitive dynamic comparator

Abstract: A new structure single-stage dynamic comparator with a large input common-mode range is proposed. The proposed comparator is compared with previous dynamic comparators. With same size input transistors and load capacitance, it is more than 1.2 times faster with <80% power consumption. Also, the input-referred noise and offset are no more than the previous comparators.

A low-offset latched comparator using zero-static power dynamic offset cancellation technique

Abstract: A low-offset latched comparator using new dynamic offset cancellation technique is proposed. The new technique achieves low offset voltage without pre-amplifier and quiescent current. Furthermore the overdrive voltage of the input transistor can be optimized to reduce the offset voltage of the comparator independent of the input common mode voltage. A prototype comparator has been fabricated in 90 nm 9M1P CMOS technology with 152 µm2. Experimental results show that the comparator achieves 3.8 mV offset at 1 sigma at 500 MHz operating, while dissipating 39 μW from a 1.2 V supply.

Low-power high-speed current comparator design

Abstract: A new current comparator is proposed that is optimised for low power consumption whilst maintaining high speed. This novel comparator design offers a reduction in power consumption of over three orders of magnitude compared with other high-speed designs, and allows picoampere current decisions at kilohertz frequencies. Circuit simulations were performed in Cadence software for a standard 0.35 mum process.

Hysteretic inductive switching regulator with power supply compensation

Abstract: A system including is plurality of resistors, a plurality of comparators, and a decoder module. The resistors are connected in series between a supply voltage and a common voltage. A first input of each comparator is connected to a reference voltage. A second input of each comparator is respectively connected to one of a plurality of nodes between the resistors. The decoder module is configured to receive an output from each comparator and to output a plurality of bits based on the output of each comparator. Each of the plurality of bits indicates a different one of a plurality of voltage ranges. A present value of the supply voltage lies in one of the plurality of voltage ranges.