Comparator applications

About: Comparator applications is a research topic. Over the lifetime, 2518 publications have been published within this topic receiving 26639 citations.

Enhancements in testing devices on burn-in boards

Abstract: A system for testing semiconductor devices on device test boards has a single tester channel connected to multiple DUTs in a loop. Outputs from DUTs are received at a comparator and latch after a period of Round Trip Delay (RTD). The comparator is connected in a parallel configuration with the return path of the loop, where the point of connection is in greater proximity to DUT output pins than the test channel and is a path different from the tester I/O driver path, thus preventing input signals from test drivers from interfering with ouput signals from DUTs that will serve as inputs to test circuitry. The time it takes a new input cycle state to reach the output comparator is long after the output from a prior cycle has been tested. A diode clamp and resistor are connected in a series with the comparator at the input stage near the comparator in order to reduce ringing at the input of the comparator, which limits tester speed. Bus-switches composed of Field Effect Transistors (FET) electrically switch the input/output (I/O) of DUTs being tested to either exclusively drive or receive trace lines, respectively, reducing DUT pin loading and thus increasing achievable testing speed. The improved testing system functions in conjunction with a system designed to perform parallel test and burn-in of semi-conductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.

Switching regulator for fixing a frequency

Abstract: A switching regulator includes a power stage, an output capacitor, a first reference voltage generator, a comparator, a constant-time trigger, a frequency-to-voltage converter, and an error amplifier. The power stage includes a first switch, a second switch coupled to the first switch, and an output inductor. The comparator is coupled to the output capacitor, and output inductor, and the first reference voltage generator. The constant-time trigger is coupled to the comparator and the power stage. The error amplifier includes a first input end coupled to the frequency-to-voltage converter, a second input end, and an output end coupled to the constant-time trigger.

Adaptive referencing analog-to-digital converter

Abstract: To provide for a higher speed operation, lower cost and less complexity in terms of manufacturing, the present invention analog-to-digital converter has feedforwards, from the more significant comparators, to the less significant comparators. As the respective outputs of the comparators change state, the voltage representing that state, for that comparator, is fed to succeeding less significant comparators. With the exception of the most significant comparator whose reference bias voltage remains static, the respective bias voltages of the rest of the successive less significant comparators are shifted, either higher or lower, as the output states of their predecessor comparator(s) change. Consequently, the respective outputs of the comparators correspond, in a binary progressive manner, to a digital word that is representative of the voltage of an input analog signal.

Pipeline analog to digital converter

Abstract: The pipeline analog-to-digital converter has a number of subsequent comparator stages ( 2 ) where the thresholds of the comparator stages are adjusted in accordance with the digital conversion results from previous stages ( 18, 28, 38 ) so as to implement a non-linear conversion scale. In particular, the pipeline analog-to-digital converter consists of a number of comparator stages ( 2 ), which operate in accordance with a common clock signal. The comparator stages are connected in series in such a way that a residue signal from a previous stage is used as input signal of a subsequent stage for comparison during the next clock period of the clock signal. At least some of said comparator stages have, according to the invention, a threshold generator ( 25, 35, 45 ) for adjusting the threshold value of the respective comparator ( 22, 32, 42 ) in accordance with comparison results of previous comparator stages ( 18, 28, 38 ).

A dynamic analysis of a latched CMOS comparator

Abstract: In the implementation of high-performance CMOS over-sampling A/D converters, high-speed comparators are indispensable. This paper discusses the design and analysis of a low-power regenerative latched CMOS comparator, based on an analytical approach which gives a deeper insight into the associated trade-offs. Calculation details and simulation results for a 20 MHz clocked comparator in a 0.5/spl mu/m technology are presented.