Computer for operations with functions

About: Computer for operations with functions is a research topic. Over the lifetime, 72 publications have been published within this topic receiving 1312 citations.

Secure processing unit systems and methods

Abstract: A hardware Secure Processing Unit (SPU) is described that can perform both security functions and other information appliance functions using the same set of hardware resources. Because the additional hardware required to support security functions is a relatively small fraction of the overall device hardware, this type of SPU can be competitive with ordinary non-secure CPUs or microcontrollers that perform the same functions. A set of minimal initialization and management hardware and software is added to, e.g., a standard CPU/microcontroller. The additional hardware and/or software creates an SPU environment and performs the functions needed to virtualize the SPU's hardware resources so that they can be shared between security functions and other functions performed by the same CPU.

Advanced Computer Arithmetic Design

Abstract: From the Publisher: The book covers recent advances in the design of computer arithmetic units. This becomes an increasingly timely issue as the underlying silicon technology enables designers to capture more system functions on fewer silicon dies. The particular functions of interest include multimedia (video and audio) applications, 3-D graphic figure manipulation, wireless communications and encrypting messages.

Specialized communications processor for layered protocols

Abstract: A special purpose communications protocol processor (CPP) provides more efficient processing of layered communications protocols--e.g. SNA (Systems Network Architecture) and OSI (Open Systems Interconnection)--than contemporary general purpose processors, permitting hitherto unavailable operations relative to high speed communication links. The CPP contains special-purpose circuits dedicated to quick performance (e.g. single machine cycle execution) of functions needed to process header and frame information, such functions and information being of the sort repeatedly encountered in all protocol layers, and uses instructions architected to operate these circuits. The header processing functions given special treatment in this manner include priority branch determination functions, register bit reshaping (rearranging) functions, and instruction address processing functions. Frame processing functions so handled include CRC (cyclic redundancy check) computations, bit insertion/deletion operations and special character detection operations.

A General Hardware-Oriented Method for Evaluation of Functions and Computations in a Digital Computer

Abstract: A parallel computational method, amenable for efficient hardware-level implementation, is described. It provides a simple and fast algorithm for the evaluation of polynomials, certain rational functions and arithmetic expressions, solving a class of systems of linear equations, or performing the basic arithmetic operations in a fixed-point number representation system. The time required to perform the computation is of the order of m carry-free addition operations, m being the number of digits in the solution. In particular, the method is suitable for fast evaluation of mathematical functions in hardware.

Multipurpose functional unit with multiply-add and format conversion pipeline

Abstract: A multipurpose functional unit is configurable to support a number of operations including multiply-add and format conversion operations, as well as other integer and/or floating-point arithmetic operations, Boolean operations, and logical test operations.