Topic

# Constraint graph (layout)

About: Constraint graph (layout) is a(n) research topic. Over the lifetime, 72 publication(s) have been published within this topic receiving 1036 citation(s).

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01 Jun 1988TL;DR: The two most frequently used symbolic layout compaction approaches, constraint graph compaction and virtual grid compaction, are reviewed in this paper.

Abstract: Symbolic layout and compaction is reaching a mature status. This is demonstrated, in part, by the recent or imminent introductions of a number of commercial symbolic layout and compaction systems. The two most frequently used symbolic layout compaction approaches, constraint graph compaction and virtual grid compaction, are reviewed in this paper. The current status of these two approaches is presented by looking at the results of the ICCD87 compaction benchmark session.

80 citations

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04 Mar 1999TL;DR: This paper presents graph based algorithms for estimating the maximum leakage power, which are pattern-independent and do not require simulation of the circuit, and compares with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.

Abstract: Low supply voltage requires the device threshold to be reduced in order to maintain performance. As the device threshold voltage is reduced, it results in an exponential increase of leakage current in the subthreshold region. The leakage power is no longer negligible in such low voltage circuits. Estimates of maximum leakage power can be used in the design of the circuit to minimize the leakage power. The leakage power is dependent on the input vector. This input pattern dependence of the leakage power makes the problem of estimating the maximum leakage power a hard problem. In this paper, we present graph based algorithms for estimating the maximum leakage power. These algorithms are pattern-independent and do not require simulation of the circuit. Instead the circuit structure and the logic functionality of the components in the circuit are used to create a constraint graph. The problem of estimating the maximum leakage power is then transformed to an optimization problem on the constraint graph. Efficient algorithms on the graph are used to estimate the maximum leakage power dissipated by a circuit. We also present comparisons with exhaustive/long simulations for MCNC/ISCAS-85 benchmark circuits to verify the accuracy of the method.

66 citations

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TL;DR: This is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously, simultaneously.

Abstract: In today's system-on-chip designs, both digital and analog parts of a circuit will be implemented on the same chip. Parasitic mismatch induced by layout will affect circuit performance significantly for analog designs. Consideration of symmetry and common centroid constraints during placement can help to reduce these errors. Besides these two specific types of placement constraints, other constraints, such as alignment, abutment, preplace, and maximum separation, are also essential in circuit placement. In this paper, we will present a placement methodology that can handle all these constraints at the same time. To the best of our knowledge, this is the first piece of work that can handle symmetry constraint, common centroid constraint, and other general placement constraints, simultaneously. Experimental results do confirm the effectiveness and scalability of our approach in solving this mixed constraint-driven placement problem.

60 citations

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Panasonic

^{1}Abstract: A constraint graph is generated by representing plural nets by using vertices and correlation in the horizontal and vertical directions among the nets by using edges. Then, clustering is conducted so that each of the vertices of the constraint graph is assigned to any one of plural layers in view of a channel height and so as to minimize the number of stacked vias. Next, routing topology is obtained on the basis of obtained clusters of the respective layers and the constraint graph, and routing patterns satisfying a design rule are obtained on the basis of the routing topology. In the clustering, the number of the stacked vias is minimized while retaining the minimum channel height in view of the final routing patterns. Accordingly, the routing patterns satisfying a desired design rule can realize a high density, resulting in a compact semiconductor integrated circuit.

50 citations

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10 Jun 2002TL;DR: A floorplanning algorithm based on sequence pair representation based on computing the longest common subsequence of a pair of weighted sequences that translates to a floorplan in O(n log log n) time, which is significantly faster than the O( n3) method operating on constraint graph.

Abstract: In this paper, we present a floorplanning algorithm based on sequence pair representation. Our floorplanner has the following important features: (1) It is explicitly designed for fixed-frame floorplanning, which is different from traditional well-researched min-area floorplanning. Moreover, we also show that it can be adapted to minimize total area. (2) It addresses the problem of handling alignment constraint which arises in bus structure. (3) It deals with performance constraint such as bounded net delay, while many existing floorplanners just minimize total wire length. (4) More importantly, even with all these constraints the algorithm is very fast in that it evaluates the feasibility of a sequence pair and translates to a floorplan in O(n log log n) time typically where n is the number of blocks and the number of constrained blocks is O(n), which is significantly faster than the O(n/sup 3/) method operating on constraint graph. Our algorithm is based on computing the longest common subsequence of a pair of weighted sequences. Experimental results on MCNC benchmark for block placement show the promise of the method.

50 citations