Showing papers on "Constraint graph (layout) published in 1987"

VLSI Layout Compaction with Grid and Mixed Constraints

Abstract: We investigate the modeling and solution techniques of VLSI layout compaction using the constraint graph approach under various practical design considerations. In particular, we extend the graph method to the compaction of VLSI layout with mixed grid constraints in addition to the usual minimum- and maximum-type constraints. This is a mixed integer problem. We show that it can be solved by the search of effectively longest paths, and a fast algorithm is presented

Nutcracker: An Efficient and Intelligent Channel Spacer

Abstract: A new algorithm for channel spacing is discussed in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass the constraint graph during the whole spacing process. We propose an efficient way to enumerate all possible jogs. Therefore, for the given channel routing topology, our algorithm yields the minimal channel height with the incorporation of contacts sliding and automatic jog insertion. In the final output, only necessary jogs are inserted, and the total wire length is minimized.

Flute an Expert Floor Planner for Full-Custom VLSI Design

Abstract: Flute is a heuristic floorplanner that operates as part of Cadre, a system of cooperating expert agents for converting a hierarchical structural description into full-custom VLSI layout. Flute is modeled on the human floorplanning process and uses a mixture of rule-based programming, state control, and algorithmic operators. Initially, a topological plan is generated by placing modules on a grid graph. From this plan, a constraint graph is prepared. This graph is solved to add geometric size and placement information to the floorplan. Though Flute handles a fairly small number of submodules at a time, it can construct a floorplan of complex VLSI layout using a hierarchical structure of ICs. Flute is implemented in Zeta-lisp on Symbolics Lisp machines.

On routability for channel routing problem

Abstract: The routing requirement in the channel routing problem for automatic wire routing in the interior of LSI is realizable if the constraint graph contains no cycle. Otherwise, the trunks for several appropriate nets must be divided into pieces. In this paper we modify a routing requirement with cyclic conflicts into one without them by dividing trunks into two parts. First we define a directed bipartite graph G to represent the routing requirement. A set of vertices in a strongly connected component in G is called a crowded set. It is shown that a routing requirement is realizable if there exists no crowded set in G. On the other hand, in the presence of a crowded set we define a method of dividing a net n contained in the crowded set into two subnets n' and n'' at some terminal position. If n' and n'' are not contained in any crowded set in the graph modified by division, we say that the division is effective. We then present a necessary and sufficient condition for the existence of effective division. Further, a semi-effective division is defined to deal with the case where there is no effective division and then the routability for the channel routing problem is discussed.

Probabilistic compaction algorithm for LSI cell layout design

Abstract: A compaction algorithm is presented that compacts LSI cell layout in a probabilistic manner The algorithm is based on the constraint graph where the edge length is iteratively changed probabilistically using parameters and random numbers Some experimental results show that an area reduction of from 2% to 20% can be achieved in comparison with the conventional compaction algorithm The algorithm can also control the aspect ratio of the compacted layout