Showing papers on "Constraint graph (layout) published in 1989"

The channel intersection problem in the building block style layout

Abstract: A new routing region definition and ordering algorithm are presented for building block layout consisting of rectangular blocks. In contrast to other works, this algorithm enables a router to deal with the channel intersections efficiently, while permitting the expansion of any region when being routed. Before this algorithm is run, it is assumed that proper routing space has been assigned between the circuit blocks, so that the expansion of a region does not greatly affect the general structure. The algorithm starts from the classic set of channels. Each channel is then decomposed into several rectangular regions. If N is the number of channels, there will be around 2N regions at the end of the process. A constraint graph defines the order in which the regions should be routed. Routing results are given to illustrate the efficiency of this new scheme. >

A hierarchical constraint graph generation and compaction system for symbolic layout

Abstract: A novel approach and system for graph-oriented layout compaction for large symbolic layout designs is presented. Hierarchical compaction is performed by generating geometrical interfaces for compacted subcells which are used as rigid nodes in graphs at higher hierarchical levels. Further reduction of the complexity of graph generation and compaction is achieved by setting only local constraints in the graphs, which requires an iterative graph-generation/compaction scheme. >

Compaction device for mask pattern data of semiconductor integrated circuit

Abstract: PURPOSE:To execute the compression with high density by detecting whether a mask pattern is equipotential or not by executing equipotential tracking and compressing a part between equipotential patterns so as to bring them as close as possible to each other without taking the minimum allowable interval into consideration. CONSTITUTION:Operations of a drawing input means 1, a group dividing means 2, a group interval determining means 4, and a drawing output means 5 are executed in the same way as an operation in a conventional device. In this state, an equipotential tracking means 6 executes equipotential tracking, and checks up whether the potential between mask patterns is equipotential or not. This processing part is processed before a constraint graph is generated by a constraint graph generating means 3, and a part between equipotential mask patterns is brought to compaction so as to bring them as close as possible to each other without considering the minimum allowable interval value designated by a pattern design rule. In such a way, mask pattern data which has been inputted is compressed with higher density, and it is facilitated to design a semiconductor integrated circuit with higher density.

Breaking cycles and vertical constraints in Deutsch's new and more difficult channel-routing problems

Abstract: In the past decade, D. Deutsch's (1976) difficult example has been used extensively as a benchmark to test various channel-routing algorithms. Since more and more channel routers are able to achieve an optimal or near-optimal solution for the original difficult example. Deutsch recently (1989) proposed two new and more difficult channel-routing problems to provide new challenges for researchers in this area. Due to off-grid terminal locations in the new examples, the number of vertical constraints are almost doubled, and many cycles are present in the vertical constraint graph. A gridless channel router which intelligently generates doglegs to break cycles and vertical constraints and successfully completes the routing of Deutsch's new and more difficult examples is presented. This gridless router is among the first routers to report results on these new benchmarks. >