Showing papers on "Constraint graph (layout) published in 1990"
11 Nov 1990
TL;DR: Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI, which allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition.
Abstract: Efficient placement and routing algorithms are presented for the modules of a bipolar analog LSI. In the layout of an analog module, a grid-free technique is required to minimize the module area and geometric constraint observance is necessary for the circuit performance optimization. The placement algorithm determines cell positions observing the geometric constraints by vertex-grouping of the constraint graph representing the relative device positions in the input circuit diagram. The routing algorithm, based on the characteristic fine-grid maze router, allows grid-free routing and variable width routings observing the geometric constraints by dynamically generating wiring prohibition. These algorithms are applied to the design of the analog modules. Automatically designed modules are compact and the performance requirements are met. >
17 citations
TL;DR: Experimental results show that the proposed system successfully accomplishes layout compaction with almost linear time complexity in terms of the rectangles in the source layout.
Abstract: This paper presents the algorithms, implementation, and performance of a hierarchical mask compactor based on a fast region-query and space-efficient data structure called the multiple storage quadtree Unlike symbolic compaction, the proposed mask compaction is based on rectangles rather than symbols A new method of generating the constraint graph by using a sweeping-line algorithm in two-dimensional space is proposed in detail Some important features of the mask compactor, such as error tolerance, mixed constraint, grid freeness, and hierarchical design and amalgamation, are described Experimental results show that the proposed system successfully accomplishes layout compaction with almost linear time complexity in terms of the rectangles in the source layout
7 citations
TL;DR: The algorithm employs a search method in the solution space, known as Simulated Annealing, and the dogleg strategy adopted is similar to that employed in the channel routing algorithm proposed in [1].
Abstract: In this paper an algorithm for the Channel Routing Problem (CRP) on the Manhattan Model is proposed. The algorithm employs a search method in the solution space, known as Simulated Annealing. The channel width is reduced by breaking up thelong runs of the vertical constraint graph, associated with the problem. The dogleg strategy adopted is similar to that employed in the channel routing algorithm proposed in [1]. The results obtained by extensive simulation runs are encouraging compared with the results of other heuristics for the same problem.
3 citations
TL;DR: An incremental algorithm to perform layout compaction is proposed that incrementally decreases the number of edges to be searched in the constraint graph.