Showing papers on "Constraint graph (layout) published in 1993"
09 May 1993
TL;DR: A novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality is described.
Abstract: The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.
20 citations
IBM1
TL;DR: This paper presents a meta-modelling framework that automates the very labor-intensive and therefore time-heavy and error-prone process of computer-aided design (CAD) design.
Abstract: Ever since commercial integrated circuits (IC) became available in the early 60s, there has been a need for computer-aided design (CAD) tools. This need is a direct consequence of two problems: firstly, the need to automate repetitive, time consuming and error-prone tasks; and secondly, the explosion in design complexity which has rendered computer tools indispensable for handling vast amounts of data.
4 citations