Showing papers on "Constraint graph (layout) published in 1998"

Simultaneous wire sizing and wire spacing in post-layout performance optimization

Abstract: In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitance in a wire are included in interconnect delay calculation. Combined with general ASIC design flow, we construct section constraint graph in each routing region and use the graph to guide segment sizing and spacing. By defining a cost function to trade-off between interconnect delay and routing area, we formulate wire sizing and wire spacing problem (WSSP) into a constraint-optimization problem and develop a heuristic algorithm to solve it. The preliminary experiments are promising.

Method for manufacturing and designing a wiring of a channel of an electronic device and electronic apparatus

Abstract: The invention relates to a method for manufacturing of electronic devices, such as very large scale integrated devices, having a channel. The channel routing is done based on a compositional approach in which initially all individual terminals are represented by individual nodes in a terminal vertical constraint graph. Individual constraints between individual terminals are represented by separate edges. This approach allows the resolution of difficult classes of routing problems in an efficient way.

Invisible edge and soft tied in compaction strategy

Abstract: In most conventional one-dimensional compaction technique, the objects are frequently tied together to reduce the computation complexity The compactness of the resulting layout may, however, be reduced when the ties appear in the critical path In this paper, this problem is solved by the soft tie which can be broken to relocate the objects position The compactness is also limited by the extra edge used to avoid diagonal constraint violation In addition, the wire terminating without any rigid object at its end can cause an additional vertex in the constraint graph The number of these wires gradually increases after jog insertion is performed in each compaction step, thus the complexity will be increased The invisible edge is proposed to solve this problem Furthermore, any necessary jogs can be inserted automatically The invisible edge and soft tie technique allows the one-dimensional compaction to gain the compactivity close to that obtained by the dimensional compaction within reasonable complexity O(N/sup 2/)

Utility function based hybrid algorithm for channel routing

Abstract: This paper presents a two layer channel router with no doglegs, based on a hybridization of Stochastic Evolution and Tabu search methods. The problem-domain knowledge expressed in the form of utility functions is used to guide the exploration of the search space. Unlike previous search heuristic based routers, the use of utility functions in our router provides a powerful tool to determine the best moves that guarantee convergence in shorter times. The algorithm begins with an initial placement of nets, generated such that the nets are in relative conformity with the vertical constraint graph. Vertical and horizontal constraints are observed during the search process. The feasibility of the ideas is demonstrated using five benchmark problems. Optimal solutions are found in each case.

A method for manufacturing and designing an electronic device and electronic apparatus

Abstract: The invention relates to a method for manufacturing of electronic devices, such as very large scale integrated devices, having a channel. The channel routing is done based on a compositional approach in which initially all individual terminals are represented by individual nodes in a terminal vertical constraint graph. Individual constraints between individual terminals are represented by separate edges. This approach allows to resolve difficult classes of routing problems in an efficient way.

Local optimality theory in VLSI channel routing: composite cyclic vertical constraints

Abstract: Local Optimality paradigm is applicable to all combinatorial optimization problems. Its direct field of application are the constructive solution algorithm; its main advantage is the low computational cost for multiple high quality initial solutions for iterative improvement algorithms. The application of the paradigm to the VLSI channel routing has necessitated the creation of new knowledge represented by the theory of locally optimal breaking (LOB) of directed circuits (DC) in the vertical constraint graph. Existing theory has supported deterministic polynomial time algorithms for LOB of two classes of directed circuits, the classes of vertex disjoint DCs, and of couples of connected DCs. The new LOB theory supports algorithms for more complex classes of any number of DCs sharing a single vertex and of a uniform lattices of DCs. It is significant that the new theory relies on the theory for couples of connected DCs for breaking more complex structures of connected DCs.