Constraint graph (layout)

About: Constraint graph (layout) is a research topic. Over the lifetime, 72 publications have been published within this topic receiving 1036 citations.

Method for optimizing track assignment in a grid-based channel router

Abstract: A method for optimal track assignment in a grid-based channel router Initially, interconnection information is extracted from a global routing result Multiple pin nets derived from the interconnection information are decomposed into simpler mapped segments A channel grid map is then built and marked with existing objects Next, a vertical constraint graph specifying the relative positions of the mapped segments is constructed A first track is computed A track assignment loop is repeated until all requisite connections are realized The track assignment loop includes the steps of breaking cycles and long paths and collecting a set of feasible links One or more weighting functions are assigned to each such feasible link A dynamic programming approach is used to select an optimal set of feasible links according to the weighting functions In addition, an optimal set of feasible links corresponding to unpreferred layers is collected by applying dynamic programming Finally, the chosen feasible links are physically realized on the current track

Integrated circuit routes designing method and apparatus

Abstract: It is intended to obtain, for a channel routing region incorporating routing prohibition figures, detailed interconnection routes that satisfy given connection requirements and minimize the area of a channel region. There are provided steps of setting a channel routing region, setting a net list N as a set of subnets obtained by dividing nets, calculating a set of assignable tracks of each subnet and other necessary sets and a route density, executing a process for avoiding a vertical passage prohibition figure that obstructs routing for a subnet whose set of assignable tracks is an empty set, generating a prohibition constraint graph G representing constraints relating to vertical passage prohibition figures and terminals, forming a prohibition constraint subgraph G* from the graph G, determining a subnet set N* as a subject of a trunks assigning process from a node set of the graph G*, assigning trunks of the subnets that belong to the set N*, updating the net list N to (N-N*) and setting a graph obtained by deleting G* from G as a new prohibition constraint graph G, and judging whether all subnets of the set N* have been assigned to tracks.

Constraint graph-based macro placement for modern mixed-size circuit designs

Abstract: In this paper, we propose a constraint graph-based macro placement algorithm that removes macro overlaps and optimizes macro positions for modern mixed-size circuit designs. Improving over the constraint graph by working only on its essential edges without loss of the solution quality, our algorithm can search for high-quality macro placement solutions effectively and efficiently. Instead of packing macros along chip boundaries like most recent previous work, our placer can determine a non-compacted macro placement by linear programming and placement region cost evaluation and handle various placement constraints/objectives. Compared with various leading academic macro placers, our algorithm can consistently and significantly reduce the wirelengths for designs with different utilization rates, implying that our macro placer is robust and has very high quality.

Algorithms for three-layer over-the-cell channel routing

Abstract: The authors present a novel algorithm for three-layer, over-the-cell channel routing of standard cell designs. The novelty of the proposed approach lies in the use of 'vacant' terminals for over-the-cell routing. Furthermore, the authors consider both the maximum cliques in the horizontal constraint graph and the longest paths in the vertical constraint graph as a basis for choosing the nets to route over the cells. They prove that their net selection algorithm is guaranteed to produce a solution within 68% of the optimum. The proposed algorithm has been implemented and tested on several benchmark examples. For the entire PRIMARY 1 benchmark, they reduce the total routing height by 76% as compared to a two-layer channel router, which leads to a 7% reduction in chip height. >

Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout

Abstract: In recent high-performance analog integrated circuit design, it is often required to place some cells symmetrically to a horizontal or vertical axis. Balasa et al. proposed a method of obtaining the closest placement that satisfies the given symmetry constraints and the topology constraints imposed by a sequence-pair (seq-pair). However, this method has the following defects: 1) Balasa's necessary condition for existence of the cell placement that satisfies the given constraints is incorrect; 2) some cells overlap; 3) the closest placement of satisfying both the symmetry and topology constraints is not always obtained; and 4) there is no explanation of placing cells symmetrically to plural axes. In this paper, we clarify the necessary and sufficient conditions for the existence of the cell placement that satisfies the given symmetry constraints and the topology constraints imposed by a seq-pair, and we propose an efficient method of obtaining, by linear programming, the closest cell placement that satisfies the given constraints. Here, a simple constraint graph is obtained from a seq-pair in order to derive a set of linear constraint expressions. Then, to shorten the running time of linear programming, the number of linear expressions is reduced by substituting the expressions for dependent variables, and the solution is obtained. The effectiveness of the proposed method was shown by computational experiments