Constraint graph (layout)

About: Constraint graph (layout) is a(n) research topic. Over the lifetime, 72 publication(s) have been published within this topic receiving 1036 citation(s).

Enhancing Engineering Design and Analysis Interoperability Part 1: Constrained Objects

Abstract: The wide variety of design and analysis contexts in engineering practice makes the generalized integration of computer-aided design and engineering (CAD/CAE) a challenging proposition. Transforming a detailed product design into an idealized analysis model can be a time-consuming and complicated process, which typically does not explicitly capture idealization and simplification knowledge. Recent research has introduced the multi-representation architecture (MRA) and analyzable product models (APMs) to bridge the CAD-CAE gap with stepping stone representations that support design-analysis diversity. This paper introduces constrained objects (COBs) as a generalization of the underlying representations. The COB representation is based on object and constraint graph concepts to gain their modularity and multi-directional capabilities. Object techniques provide a semantically rich way to organize and reuse the complex relations and properties that naturally underlie engineering models. Representing relations as constraints makes COBs flexible because constraints can generally accept any combination of I/O information flows. This multi-directionality enables design sizing and design verification using the same COBbased analysis model. Engineers perform such activities through out the design process, with the former being characteristic of early design stages and vice versa. This paper presents basic examples to illustrate the main COB concepts. To validate the COB representation, other work describes electronic packaging and aerospace test cases implemented in a toolkit called XaiTools ™ . In all, the test cases utilize some 260 different types of COBs with some 370 relations, including automated solving using commercial math and finite element analysis tools. Results show that the COB representation gives the MRA a more capable foundation, thus enhancing physical behavior modeling and

Symbolic Layout Compaction

Abstract: Many experienced hand layout designers plan their layout by first rearranging the circuit topology in a way that they believe will result in the best final layout. The rearranged configuration is often drawn as a rough diagram indicating the desired placement of circuit elements and interconnection lines. Such a rough layout plan is then used as a guide during the tedious and error-prone actual layout process to remind the designer of the intended space utilization. In the past few years, layout plans of this type have become known as “stick diagrams” [1, 2] for they contain mostly simple line drawings.

A hierarchical methodology to improve channel routing by pin permutation

Abstract: A hierarchical pin permutation algorithm is presented which is used as a preprocessor of conventional channel routing algorithms. This algorithm determines the proper positions of permutable gates and cell terminals such that the results of the subsequent channel routing can be significantly improved. First, gates and terminals are interchanged to maximize the number of aligned terminal pairs and to reduce the channel density. Then, terminals that are not aligned are interchanged to remove cyclic constraints in the vertical constraint graph (VCG). Experimental results show that the proposed algorithm considerably reduces the number of tracks and vias. >

An Efficient Graph-Based Algorithm for ESD Current Path Analysis

Abstract: The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer-circuit design. High voltages that resulted from ESD might cause high current densities in a small device and burn it out, so on-chip protection circuits for IC pads are required. To reduce the design cost, the protection circuit should be added only for the IC pads with an ESD current path, which causes the ESD current path analysis problem. In this paper, we first introduce the analysis problem for ESD protection in circuit design. We then model the circuit as a constraint graph, decompose the ESD connected components (ECCs) linked with the pads, and apply breadth-first search (BFS) to identify the ECCs in each constraint graph and, thus, the current paths. Experimental results show that our algorithm can very efficiently and economically detect all ESD paths. For example, our algorithm can detect all ESD paths in a circuit with more than 1.3 million vertices in 1.39 s and consume only 44-MB memory on a 3.0-GHz Intel Pentium 4 PC. To the best of our knowledge, our algorithm is the first point tool available to the public for the ESD analysis.

Synthesis of ASICs with Hercules and Hebe

Abstract: Computer-aided synthesis of digital circuits from behavioral specifications offers an effective means of dealing with the increasing complexity of digital hardware design. The benefits of such a methodology include shortened design time to reduce design cost, ease of modification of the hardware specifications to enhance design reusability, and the ability to more effectively and completely explore the different design tradeoffs between area of the resulting hardware and its processing time.