Showing papers on "Contact resistance published in 1991"

Performance of thin hydrogenated amorphous silicon thin‐film transistors

Abstract: In this paper we have analyzed the influence of the mask channel length (LM) on the performance of the 55‐nm‐hydrogenated amorphous silicon (a‐Si:H) thin‐film transistors (TFTs), incorporating nitrogen‐rich hydrogenated amorphous silicon nitride gate dielectric and phosphorus‐doped microcrystalline silicon (n+μc‐Si:H) source/drain (S/D) contacts. In our TFTs the n+μc‐Si:H S/D contacts have a specific contact resistance around or below 0.5 Ω cm2. We have shown that in our TFTs a field‐effect mobility and threshold voltage are dependent on LM, and this dependence is most likely due to the influence of the S/D contact series resistance on TFTs characteristics. Finally, we have demonstrated that if the mask channel length is extended by a ΔL (which is a distance from the S/D via edge at which the electron injection/collection is taking place) the field‐effect mobility and threshold voltage are independent of the channel length. In such a case μFE, VT, and ON/OFF current ratio around 0.76 cm2/V s, 2.5 V, and 1...

Electrical contacts and method of manufacturing same

Abstract: A known rear contact construction on silicon solar cells comprises aluminum contacts with silver soldering pads. According to this invention, nickel is introduced into the contact construction to reduce the contact resistance between the aluminum contact material and the silver pads. In one embodiment, the nickel is applied as an intermediate layer (32) between the silicon substrate (2) and each silver pad (20). In a second and preferred embodiment, the nickel is incorporated into the silver ink that is used to make the soldering pads.

Semiconductor device with ferroelectric and method of manufacturing the same

Abstract: The structural body of a ferroelectric capacitor C is located over a source region (23) between a gate electrode (22) and a local oxide film (26). The structural body has a ferroelectric film (29) and an upper electrode (30) and a lower electrode (31) for sandwiching the ferroelectric film (29), and is provided with a conductive oxide film (32) between the lower electrode (31) and the source region (23). The conductive oxide film (32) is ITO, ReO 2 , RuO 2 or MoO 3 . If an oxygen anneal is conducted after forming the ferroelectric film (29) for the purpose of reforming crystallizability of the ferroelectric film (29), oxygen enters into the conductive oxide film (32) to some extent. As a result, the conductive oxide film (32) is further oxidized, and becomes a so-called oxide barrier or dummy layer. Therefore, formation of a silicon oxide film hardly occurs on the source interface, reduction of contact resistance and avoidance of series parasitic capacitance can be attained, the degree of freedom of the capacitor C forming region is increased, and a high density integration can be schemed.

Electrical characteristics and reliability of Pt/Ti/Pt/Au ohmic contacts to p-type GaAs

Abstract: The ohmic contacts to p-type GaAs formed by GaAs/Pt/Ti/Pt/Au systems were investigated. The specific contact resistance below 8×10-7 Ωcm2 was achieved when the interface Pt between GaAs and Ti/Pt/Au was thicker than 50 A, which is about one-fourth of the conventional Ti/Pt/Au contact. The activation energies of the initial degradation of the Pt/Ti/Pt/Au electrodes correspond to the reaction of GaAs and Pt to form PtAs2. However, even after the initial degradation, Pt/Ti/Pt/Au with the thin Pt interface layer still shows lower contact resistivity. These systems are promising for practical p-tye ohmic contacts for AlGaAs/GaAs heterojunction bipolar transistors.

Measurement of collector and emitter resistances in bipolar transistors

Abstract: New DC methods to measure the collector resistance R/sub C/ and emitter resistance R/sub E/ are presented. These methods are based on monitoring the substrate current of the parasitic vertical p-n-p transistor linked with the n-p-n intrinsic transistor. The p-n-p transistor is operated with either the bottom substrate-collector or the top base-collector p-n junction forward-biased. This allows for a separation of the various components of R/sub C/. R/sub E/ is obtained from the measured lateral portion of R/sub C/ and the collector-emitter saturation voltage. Examples of measurements on advanced self-aligned transistors with polysilicon contacts are shown. The results show a very strong dependence of R/sub C/ on the base-emitter and base-collector voltages of the n-p-n transistor. The bias dependence of R/sub C/ is due to the conductivity modulation of the epitaxial collector. From the measured emitter resistance R/sub E/ a value for the specific contact resistance for the polysilicon emitter contact of rho /sub c/ equivalent to 50 Omega - mu m/sup 2/ is obtained. >

DC Conductivity of Li1.3Al0.3Ti1.7(PO4)3 Ceramic with Li Electrodes.

Abstract: The ionic conductivity of a solid electrolyte, Li1.3Al0.3Ti1.7(PO4)3, was measured with Li and Li–Al alloy electrodes. The contact resistance between the Li electrode and the electrolyte was a dominant factor for the DC conductivity. A higher DC conductivity was obtained by an utilization of the Li4Al alloy electrodes.

An investigation of the Pd‐In‐Ge nonspiking Ohmic contact to n‐GaAs using transmission line measurement, Kelvin, and Cox and Strack structures

Abstract: The Pd‐In‐Ge nonspiking Ohmic contact to n‐GaAs has been investigated using the transmission line, the Kelvin, and the Cox and Strack structures. It has been found that a layered structure of Pd/In/Pd/n‐GaAs with 10–20 A of Ge imbedded in the Pd layer adjacent to the GaAs can lead to a hybrid contact. When the Ohmic formation temperature is above 550 °C, a layer of InxGa1−xAs doped with Ge is formed between the GaAs structure and the metallization. When the Ohmic formation temperature is below 550 °C, a regrown layer of GaAs also doped with Ge is formed at the metallization/GaAs interface. The contact resistivity of 2–3×10−7 Ω cm2 for this contact structure is nearly independent of the contact area from 900 to 0.2 μm2. Low‐temperature Ohmic characteristics and thermal stability are also examined.

Contact sidewall tapering with argon sputtering

Abstract: The method for making a contact opening for an integrated circuit having a feature size of about one micrometer or less is accomplished by first providing an integrated circuit structure having device elements within a semiconductor substate and multilayer insulating layers thereover. A resist masking layer is formed over the multilayer insulating layer having openings therein in the areas where the contact openings are desired. Isotropic etching is done through a desired thickness portion of multilayer insulating layer. Anisotropic etching is now done through the remaining thickness of multilayer insulating layer to the semiconductor substrate to form the desired contact opening. The resist layer is removed. The structure is subjected to an Argon sputter etching ambient to smooth the sharp corners at the upper surface of multilayer layer and the point where the isotropic etching ended and the anisotropic etching began. It is preferred that soft reactive ion etching be done for a period of less than about 30 seconds after said Argon sputter etching to reduce the increased contact resistance caused by this Argon sputter etching.

The Influence of Interstitial Ga and Interfacial Au (sub 2)P (sub 3) on the Electrical and Metallurgical Behavior of Au-Contacted III-V Semiconductors

Abstract: The introduction of a very small amount of Ga into Au contact metallization on InP is shown to have a significant effect on both the metallurgical and electrical behavior of that contact system. Ga atoms in the interstices of the Au lattice are shown to be effective in preventing the solid state reactions that normally take place between Au and InP during contact sintering. In addition to suppressing the metallurgical interaction, the presence of small amounts of Ga is shown to cause an order of magnitude reduction in the specific contact resistivity. Evidence is presented that the reactions of GaP and GaAs with Au contacts are also drastically affected by the presence of Ga. The sintering behavior of the Au-GaP and the Au-GaAs systems (as contrasted with that of the Au-InP system) is explained as due to the presence of interstitial Ga in the contact metallization. Finally the large, two-to-three order of magnitude drop in the contact resistance that occurs in the Au-InP system upon sintering at 400 degrees Centigrade is shown to be a result of the formation of an Au (sub 2) P (sub 3) layer at the metal-semiconductor interface. Contact resistivities in the 10 (sup -6) ohm square centimeter range are obtained for as-deposited Au on InP when a thin (20 Angstrom) layer of Au (sub 2) P (sub 3) is introduced between the InP and the Au contacts.

Thermal Rectification in Similar and Dissimilar Metal Contacts

Abstract: An investigation was conducted to verify experimentally the existence of thermal rectification and to determine the effect of surface roughness and material type. Four pairs of test specimens were evaluated: one with a smooth Nickel 200 surface in contact with a rough Nickel 200 surface, one with a smooth Stainless Steel 304 surface in contact with a rough Stainless Steel 304 surface, one with a smooth Nickel 200 surface in contact with a rough Stainless Steel 304 surface, and finally, one with a smooth Stainless Steel 304 surface in contact with a rough Nickel 200 surface. The thermal contact conductance was measured for heat flow from both the smooth to rough and rough to smooth configurations for all four parts. The results indicate that thermal rectification is a function of surface characteristics, material type, and heat flow direction. For similar materials in contact, some thermal rectification was observed with heat flow from the rough surface to the smooth surface resulting in a higher value of contact conductance. For dissimilar materials, the thermal contact conductance was highest when the heat flow was from the Stainless Steel 304 to Nickel 200. In these cases, the surface roughness was shown to be ofmore » secondary importance.« less

Conductive fine-grain, electrode connection structural body and manufacture thereof

Abstract: PURPOSE:To provide conductive fine-grains having improved reliability in the connection with electrodes and reducing the contact resistance CONSTITUTION:A conductive fine-grain 9 consists of a base fine-grain 3, an inside metal layer 2, of which melting point is not less than 900 degC, provided on the surface of the fine-grain 3, and an outside metal layer, of which melting point is not more than 350 degC, provided on the outside of the inside metal layer 2 When each conductive fine-grain 9 is arranged and heated between each pair of electrodes 4, 5 opposite to each other, the outside metal layer of each conductive fine-grain 9 is fused and stuck to the electrodes 4, 5 By this sticking, a contact area between the electrodes 4, 5 and each conductive fine-grain 9 is increased On the other hand, since the inside metal layer 2 is on the surface of the base fine-grain 3, connection reliability between each conductive fine-grain 9 and the electrodes 4, 5 is improved and a contact resistance is also reduced

Pd/Zn/Pd/Au ohmic contacts to p -type InP

Abstract: Low resistance ohmic contacts (ρc = 7 x 10-5 Ω-cm2) have been fabricated to Zn-doped p-type InP using an annealed Pd/Zn/Pd/Au metallization. Palladium reacts with InP at low temperatures to form a Pd2InP ternary phase, which is initially amorphous but crystallizes and grows epitaxially on InP. Zinc reacts with some of the overlying Pd to form PdZn (≅250° C), which decomposes at 400-425° C to form PdP2, freeing up Zn to diffuse into Au as well as InP. The contact resistance reaches a minimum as the decomposition reaction takes place. The resultant ohmic contact is laterally uniform and consists of epitaxial Pd2InP adjacent to InP, followed by a thin layer of PdP2 and then the outer Au layer. Further annealing leads to a breakdown of the contact structure,i.e. decomposition of Pd2InP, and an increase in contact resistance.

Minimal ohmic contact resistance limits to n‐type semiconductors

Abstract: An exact general formula for the lower contact resistance limit is derived, giving the lowest possible ohmic contact resistance for nondegenerate and degenerate metal‐semiconductor contacts. Calculations for nondegenerate semiconductors include the nonparabolic nature of the conduction‐band electrons and full Fermi–Dirac statistics. A discussion of standard emission theories shows that they are not applicable in the ohmic contact limit because of ‘‘electron tail lowering’’ and the negligence of quantum‐mechanical reflections due to occupied states on the opposite side of their derivation. Together with a proof that an abrupt n‐n+ doping step is governed by thermionic emission, the ohmic contact resistance of a general ohmic contact is determined and it is shown that the n‐n+ doping step is responsible for this limitation. Thus, the lowest possible contact resistance is determined by the bulk doping of the semiconductor for a large variety of different alloyed and nonalloyed contact structures and not by t...

Electric contact materials and their erosion in automotive DC relays

Abstract: Proper contact material selection is critical for reliable performance of automotive relays. Three types of contact material were compared in a 20-A relay, which were switching lamp, motor, and resistor loads. The three contact materials chosen have different material strengthening mechanisms so that their effects on the arc erosion process could be evaluated. They include: (a) a silver alloy (98Ag-2Cu), (b) a metal-oxide composite (Ag-SnO/sub 2/ with WO/sub 3/ additive), and (c) a metal-metal composite (Ag-20Ni). Contact resistance, welding, and DC transfer characteristics were compared in make-only, break-only, and normal make-and-break switching operations. The observed results were explained in terms of the arc erosion process and inherent material structures. All three types of contact material have their own pros and cons in automotive applications. >

Method of reducing contact resistance at silicide/active area interfaces and semiconductor devices produced according to the method

Abstract: Disclosed is a semiconductor processing method for reducing contact resistance between an active area and an overlying silicide resulting from diffusion of an impurity from the active area into the silicide. The method comprises implanting germanium through the contact opening and into the active area of the wafer to a peak density at an elevation which is at or above the elevation of the peak density of the conductivity enhancing impurity. A layer of metal is applied atop the wafer and into the contact opening to contact the active area. The metal and silicon within the contact opening are annealed to form a metal silicide. The annealing step consumes elemental silicon into the wafer to an elevation which is at or above the elevation of the germanium peak density. The germanium restricts diffusion of the conductivity enhancing impurity therethrough during the silicide anneal.

Method of providing lower contact resistance in MOS transistor structures

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Improvement of ohmic contacts on GaAs with in situ cleaning

Abstract: An in situ argon ion mill clean step prior to ohmic metal deposition has been demonstrated to improve the uniformity of the contact parameters and reduce the contact resistance. After ion mill cleaning, the native oxide regrowth of molecular beam epitaxy grown GaAs and AlGaAs layers in vacuum chamber was also studied to optimize the processing. These oxide layers were identified as the cause of problems in the formation of good ohmic contacts to the GaAs or AlGaAs.

The importance of the thickness of silver coating in the corrosion behaviour of copper contacts

Abstract: The deterioration mechanisms of unplated and silver-plated copper contacts subjected to corrosive environments have been studied. The influence of the surface treatment and the silver coating thickness was investigated in a short-time test in a flowing mixture of three gases. The influence of brighteners and chromate passivation of the silver coating was also studied. In addition to contact resistance measurements at different normal loads, Auger electron microscopy was used to study the processes involved. Short-time testing in a flowing mixture of three gases proved to be a valuable means for investigating the performance of electrical contacts. It is concluded that the silver coating thickness is the most important factor in corrosion resistance. Contacts with a thin silver coating behave almost like ground unplated copper contacts. >

Magnetic field sensor contacts

Abstract: A magnetic field sensor, such as a magnetoresistor, Hall effect device or magnetotransistor, comprising an active layer of indium antimonide on the surface of a substrate having a length substantially greater than its width. A conductive contact is on the active layer at each end thereof and a plurality of shorting bar contacts are on the active layer and spaced along the length of the active layer between the end contacts. The contacts are each of a thin layer of a highly conductive n-type conductivity semiconductor material which has a low sheet resistivity and a low contact resistance with the active layer. A layer of a conductive metal may be provided on the semiconductor material layer of the contact, and a thin layer of highly conductive n-type indium antimonide may be provided between the semiconductive material layer and the active layer.

Ohmic contact to n-type bulk and δ doped Al0.3Ga0.7As/GaAs MODFET type heterostructures and its applications

Abstract: A NiGeAu based metal composition with a Pt layer, has been developed for the ohmic contact to n -type bulk and δ doped Al 03 Ga 07 As/GaAs MOdulation Doped Field Effect Transistor (MODFET) type heterostructures This composition provides a smooth surface morphology, an edge definition better than 01 μm and reproducible electric properties after Rapid Thermal Annealing (RTA) Undoped cap layer MODFET heterostructures with spacer thickness varying from 5 nm to as high as 100 nm have been investigated Ohmic contact behavior of bulk and δ doped heterostructures with 5 nm spacer layers are compared The contact resistances obtained for these structures range between 01 and 25 Ω mm at room temperature, and remain unchanged down to 4 K The advantages of this contact will be illustrated in two applications

Ohmic contacts to p-GaAs with p + /p regrown structures formed by metalorganic molecular beam epitaxy

Abstract: Excellent ohmic contacts to p‐GaAs are fabricated using selective growth by metalorganic molecular beam epitaxy. Specific contact resistance of about 5×10−8 Ω cm2 is achieved, without any heat treatment, at AuMn/Au and Ti/Pt/Au metal contacts, formed on p+‐GaAs layers heavily carbon‐doped to 4.4×1020 cm−3. Regrown contacts with planar and lateral p+/p structures are fabricated to clarify interface contact resistivities. A fairly low value of 7.1×10−8 Ω cm2 is established, using an equivalent circuit model, for the lateral contacts to thin p‐GaAs layers, reasonably independent of its thicknesses in the range of 9.5–95 nm. These results, in addition to excellent growth selectivity, have confirmed prospects for practical use.

Contact metallization of semiconductor integrated circuit devices

Abstract: In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide is intermediary to silicon and metal. The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material, and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g., in dynamic random-access memory arrays.

An eight-terminal Kelvin-tapped bipolar transistor for extracting parasitic series resistances

Abstract: A novel DC method for determining the components of series resistance in bipolar transistors is presented. As a DC technique, it shows unprecedented accuracy as demonstrated by its application to both metal-contacted heterojunction transistors and more conventional bipolar junction transistors (BJTs). The measurement error was minimized by using a single double-base Kelvin-tapped transistor to extract all components of series resistance. This extraction technique was applied to transistors from an industrial poly-contacted BJT process with various geometries. The authors describe the theory and application of this extraction technique in both its simplified form, where the emitter resistance is assumed to be lumped and bias-independent, and in its more general form, where it includes the distributed nature of both the emitter and the intrinsic base resistances. An exact expression for the DC and AC bias-dependent intrinsic base resistance and a methodology for calculating effective resistances for bipolar devices are presented. >

High energy intermittent power connector

Abstract: The apparatus and method disclosed herein relates to axially aligned electrical contacts which connect a high electrical power pulse forming network to an electrothermal ammunition integrated plasma injector in a combustion augmented plasma gun for launching projectiles thereof. The contacts transfer high energy, intermittent pulses without arcing because structure provides for axially preloading the contacts to reduce contact resistance, for axially stiffening the contacts to eliminate contact bounce and for providing complementary conical contact surfaces to facilitate a high current density transfer.

Fabrication of high-conductivity, transparent electrodes with trenched metal bus lines

Abstract: A novel transparent electrode system has been developed for thin film electroluminescent displays in which the poor conductivity of the indium-tin-oxide (ITO) electrodes has been augmented by high-conductivity buses of thick a luminum or silver. The augmented electrode system consists of patterned ITO electrodes, 200 Fm wide, centered over narrow aluminum or silver lines 40 ~m wide and separated by an intermediate diffusion barrier film of t i tanium to promote adhesion to the ITO and prevent blackening of the main ITO electrode by interfacial reactions. The sheet resistances of the augmented ITO electrodes (A1-Ti-ITO and Ti-Ag-Ti-ITO) were lowered by two orders of magnitude relative to the unaugmented ITO electrodes, yielding absolute values on the order of 0.1 ~/s. Indium-tin-oxide (ITO) is the most widely used material for the transparent electrodes in alternating current-thin film electroluminescent (ACTFEL) displays (1-3). Speed and brightness uniformity depend critically on ITO line resistance, particularly for large-area displays. Even with integrated ITO lines, a 'zebra' pattern of brightness contrast occurs due to high line resistance. Therefore, to achieve higher conductivity of the transparent electrodes in ACTFEL panels, a structure was developed in which the low-conductivity ITO electrodes were augmented by buses of thick, narrow, high-conductivity metals. Not only would higher conductivity transparent electrodes reduce line delay in larger panels, but they would reduce the power consumption in these low current-high voltage devices and increase the brightness of existing displays by allowing them to be driven at much higher frequencies (4). Currently, ITO electrodes exhibiting >85% transmission in the visible spectrum and sheet resistances of 5-20 ~/[] are possible, with film thicknesses greater than 500 nm (5). However, when ITO film thicknesses in the range of 100150 nm are employed, the sheet resistance increases to levels of 30-90 ~/[~ (6). Since sheet resistances on the order of 1 ~/[~ are necessary for large-area displays, only very thick ITO lines will yield the desired properties. This is due in part to the dissipation caused by capacitive currents in highly resistive material. These thick lines lead to dielectric breakdown at the edges of the patterned ITO due to enhanced field effects and poor step edge coverage of the overlying films in the ACTFEL stack (7). A cross section of a typical pixel in an ACTFEL device, indicating where breakdown is likely to occur, is shown in Fig. i. To avoid premature breakdown at step edges, Ketchpel and Wu (7) employed a thick film aperture layer-bus rail structure for the rear aluminum electrode. A thick film insulator layer, aligned over the step edge, removed the parallel bus rail conductor in this structure from the high electrical field applied to the emitter. Our augmented electrode structure differs from this one in that a trenched metal bus rail was fabricated within the surface layers of the glass. The augmented electrode structure developed to achieve higher conductivities is shown in Fig. 2. Here, low conductivity ITO electrodes 200 ~m wide were centered over 40 ~tm wide metal bus lines. The electrode structures evaluated in this study included ITO, AI-ITO, AI-Ti-ITO, Ti-Ag-ITO, and Ti-Ag-Ti-ITO. To prevent interdiffusion of the aluminum/silver and ITO during subsequent heattreatment steps, and to promote adhesion of these metals * Electrochemical Society Active Member. 2070 to the glass and ITO, intermediate thin films of t i tanium were employed. Blackening of the transparent ITO lines has been observed during the deposition of dielectrics onto ITO (8). Here, the reduction of ITO occurs by displacement reactions with metals that form more stable oxides than indium oxide and tin oxide at the deposition temperature. Consequently, another role of the intermediate barrier film is to minimize the formation of insulating oxide films between the ITO and the bus metallization. These oxide films could lead to undesirable contact resistances and higher sheet resistances for the composite electrode structure. Ti tanium was first proposed as a contact material between A1 and Si in 1972 and was reported to have good diffusion barrier properties (9). However, this t i tanium metallurgy produced interfacial reactions with A1 which consumed the thin Ti layers at elevated temperatures and resulted in the formation of TiA13 intermetallics (10). It was reported in this study that annealing at 500~ consumed as much as 1500/~ of t i tanium in 30 min. In a more recent study of the electrical properties of this A1/Ti contact metallurgy (11), the contact resistance increased with increasing annealing temperatures, suggesting that the growth of this TiA13 intermetallic layer was a function of time at temperature. Therefore, if a thin layer of t i tanium is to be used as a diffusion barrier between the a luminum bus metal and ITO, it must be thick enough to survive any subsequent annealing steps. Historically, the system Ag-Ti and later Ag-Pd-Ti was used extensively as the metallurgy for high-intensity solar rear aluminum eleclrode 7 ~ dieleclric/~ and ~, phosphor x, ~

Method and system for concurrent electronic component testing and lead verification

Abstract: A system (100) proceeds to test and verification of simultaneous son of an electronic component (104) having two son (126 and 128). The system includes a circuit (114 and 116) determining a sum of amounts of contact resistances between first (132) and second (134) probes and a son producing a current (I1) propagating in the first probe, the yarn component, and the second probe. The sum of the contact resistance is proportional to the voltage difference between the son. If the difference exceeds a limit, then the sum of the amount of contact resistance is excessive. The system also includes a circuit (110) for determining a value of a component of the parameter while the sum of the amounts of contact resistances is determined. The sum of the circuit for determining the contact resistance and the determination of the parameter value circuit are electrically insulated from each other so that they mutually influence by.

Al-PLAPH (Aluminum-PLANarization by Post-Heating) process for planarized double metal CMOS applications

Abstract: Contact planarization in ULSI multi-level interconnections has been achieved by using a newly developed contact filling technology called Al-PLAPH (Aluminum-Planarization by Post-Heating). In the Al-PLAPH process, Al was initially deposited at room temperature without any substrate bias followed by an annealing step without breaking vacuum. In-situ annealing was carried out at a temperature range of 400 degrees C approximately 550 degrees C in a vacuum-isolated modular sputtering system. Sub-micron contacts with high-aspect-ratio (>or=1) were completely filled by heating above 500 degrees C. The process has been applied to a full CMOS device which did not show any degradation of electrical characteristics such as contact resistance and junction leakage. Reliability tests with line test patterns revealed better electromigration resistance with enhanced stress migration tolerance than conventionally grown Al lines. >

Correlations between film properties and microwave surface resistance for YBa2Cu3O7−δ thin films on MgO

Abstract: Epitaxial YBa2Cu3O7−δ thin films grown by laser ablation on MgO (100) substrates were investigated for microwave applications. By systematically varying the growth conditions, we obtained films with various microstructures, low‐frequency superconducting properties, and microwave performance. The surface resistances were determined from a measured unloaded quality factor in a 8.6‐GHz microstrip resonator. Surface resistance was found to correlate most directly with the degree of grain alignment as revealed by electron channeling and x‐ray diffraction studies. Films grown at optimal conditions gave a scaled surface resistance of 0.6 mΩ at 77 K and 10 GHz.