Showing papers on "Contact resistance published in 1992"

An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

Abstract: The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a‐Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion‐implanted n+ S/D regions. Self‐consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage‐modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.

Graded band gap ohmic contact to p‐ZnSe

Abstract: We describe a low‐resistance quasi‐ohmic contact to p‐ZnSe which involves the injection of holes from heavily doped ZnTe into ZnSe via a Zn(Se,Te) pseudograded band gap region. The specific contact resistance is measured to be in the range of 2–8×10−3 Ω cm2. The graded heterostructure scheme is incorporated as an efficient injector of holes for laser diode and light emitting diode devices, demonstrating the usefulness of this new contact scheme at actual device current densities.

Electrochemical Impedance Spectra and Deterioration Mechanism of Metal Hydride Electrodes

Abstract: Electrochemical impedance spectrum of a metal hydride electrode was interpreted by an equivalent circuit including a reaction resistance on the alloy surface, a contact resistance between the current collector and the pellet, one related to alloy particle‐to‐particle contact, and a Warburg impedance. According to the interpretation, deterioration of a metal hydride electrode using copper‐coated alloy powder was found to be caused by passivation of the alloy surface only. On the other hand, deterioration of an electrode using uncoated alloy was dominated by increase of the contact resistances.

Manufacture of semiconductor device

Abstract: PURPOSE:To restrain an increase in the contact resistance of a titanium silicide with an impurity diffusion layer by a method wherein a metal film by a mixture composed of titanium and of boron and the titanium silicide containing boron are formed on the surface of the impurity diffusion layer. CONSTITUTION:An element isolation region 2 and a P-type impurity diffusion layer 3 are formed on a semiconductor substrate 1 composed mainly of silicon; after that, a metal film 4 by a mixture composed of titanium and boron is formed on the surface of the substrate 1. Then, the film 4 is reacted with the substrate 1 in the atmosphere of an inert gas; a heat treatment is executed for a short time; a metal in a part coming into contact with the substrate 1 composed mainly of silicon, i.e., in an active element region, is reacted with the silicon; a titanium silicide 5 containing boron is formed. When the substrate 1 is treated with a mixed solution composed of ammonia water and of hydrogen peroxide water, the titanium silicide 5 can be formed, in a self-aligned manner, on the layer 3 as the active element region. Thereby, the contact resistance of the layer 3 with the titanium silicide is not increased, and it is possible to eliminate that the contact resistance becomes unstable due to the influence by the temperature of a heat treatment or the like.

Indium tin oxide as transparent electrode material for ZnSe‐based blue quantum well light emitters

Abstract: Sputter deposited indium tin oxide layers have been used as the top contact for blue LEDs and diode lasers in (Zn,Cd)Se/Zn(S,Se) quantum well heterostructures. The contact resistance to n‐Zn(S,Se) is comparable to that with indium or gold. The optically transparent contacts have been utilized, as an example, in the fabrication of a numeric display device and to show that LED emission is of excitonic origin in these type I quantum wells.

The use of an interface anneal to control the base current and emitter resistance of p-n-p polysilicon emitter bipolar transistors

Abstract: The effects of an interface anneal on the electrical characteristics of p-n-p polysilicon-emitter bipolar transistors are reported. For devices with a deliberately grown interfacial oxide layer, an interface anneal at 1100 degrees C leads to a factor of 15 increase in base current, and a factor of 2.5 decrease in emitter resistance, compared with an unannealed control device. These results are compared with identical interface anneals performed on n-p-n devices, and it is shown that the increase in base current for p-n-p devices is considerably smaller than that for the n-p-n devices. This result is explained by the presence of fluorine in the p-n-p devices, which accelerates the breakup of the interfacial layer. >

Thermally stable non‐gold Ohmic contacts to n‐type GaAs. I. NiGe contact metal

Abstract: ‘‘Nongold’’ NiGe Ohmic contacts were developed by a lift‐off and annealing technique that was extensively used to fabricate the conventional AuGeNi contacts. The optimum conditions to prepare thermally stable, low resistance NiGe Ohmic contacts were determined by changing the Ge concentrations of the NiGe contacts from 13 to 43 at. %, and the deposition sequences of the Ni and Ge layers. Contact resistances of ∼0.8 Ω mm were obtained for both two‐layered Ni/Ge and three‐layered Ni/Ge/Ni contacts, with Ge concentrations of ∼38 at. % after annealing at 600 °C. The thermal stability of the electrical properties during subsequent annealing at 400 °C after contact formation was found to be influenced by the microstructure at the GaAs/metal interface. The excellent stability was obtained only when the NiGe contacts formed high melting point NiGe compounds. The present result indicated that removal of Au from the AuGeNi contacts was not satisfactory enough to improve the thermal stability of the AuGeNi contacts after contact formation. A model for the current transport mechanism through the GaAs/NiGe interface was also proposed by correlating the electrical properties and the microstructure. This model explained well the dependences of the contact resistances on the Ge concentrations and the deposition sequence of the Ni and Ge layers.

High wattage surface contact resistance heater

Abstract: A pliable high wattage electrical resistance contact heater which is operable at two wattage densities and which includes a first heating element which is thermostatically controlled so as to activate at predetermined ambient and/or surface temperatures and a second overlapping heating element which is continuously activated when the heater is connected to a source of electrical power supply.

Method of providing lower contact resistance in MOS transistors

Abstract: Germanium is used to significantly enhance the drift mobilities of minority carriers in the channels of N-channel and P-channel metal-oxide-semiconductor (MOS) transistors with silicon substrates. Germanium processing is also used to enhance the source/drain contact conductance for MOS devices. Methods are disclosed for forming the germanium-rich interfacial layer utilizing a germanium implant and wet oxidation or growing a silicon-germanium alloy by molecular beam epitaxy.

Investigation of AuGeNi contacts using rectangular and circular transmission line model

Abstract: The effect of sheet resistance of the contact metal on the contact resistance measurement has been explored using circular-geometry transmission-line structures. Ohmic contacts of AuGeNi and AuGe/Ni/Pd/Au combination were investigated by using electrical and X-ray diffraction measurements.

Collimated sputtering of TiN/Ti liners into sub‐half‐micrometer high aspect ratio contacts/lines

Abstract: In situ sputtering of TiN/Ti liners into high aspect ratio (six to eight) sub‐half‐micrometer contacts with step coverages more than 40% on the side as well as on the bottom is demonstrated for the first time. The process utilizes a collimator, honeycomb‐like structure through which atoms are directed into contact holes. A study of step coverages, deposition rates, contact resistances, and junction leakages for Ti and TiN layers as a function of the aspect ratio of the collimator is carried out. The extendibility of collimation beyond 0.25 μm contact geometries is demonstrated. The optimum deposition rate is achieved based on the aspect ratio of the collimator. The structures formed with chemical vapor deposition (CVD) of W on TiN/Ti liners exhibit an order of magnitude improvement in contact resistance over the structures formed without collimated liners, especially for geometries below a critical geometry. The reverse leakages using the shallow junctions (0.12–0.14 μm) remain unchanged.

Intermetallic compounds at aluminum-to-copper and copper-to-tin electrical interfaces

Abstract: The effects of intermetallic compounds on the electrical and mechanical properties of bimetallic friction welded Al-Cu joints and tin-plated copper wire conductors are studied. The formation and growth of intermetallic compounds are studied in the temperature range 200-525 degrees C for the Al-Cu system, and 80 degrees -200 degrees C for the Cu-Sn system. The formation and growth of intermetallic phases exert a pronounced effect on the mechanical (microhardness) and electrical integrity of these systems. In the case of aluminum-to-copper bimetallic contacts, the contact resistance increases linearly with the thickness of the intermetallics, while in the tin-plated copper system, the resistance shows a tendency towards stabilization when the thickness of intermetallic phases approaches that of the plating. In the aluminum-to-copper joints, the presence of an electrical field greatly accelerates the kinetics of formation of intermetallic phases and significantly alters their morphology. >

Symmetric self-aligned processing

Abstract: A method of manufacturing a semiconductor device using simplified processing and eliminating and/or minimizing the extrinsic parasitic elements of the device. The method is particularly suited for manufacturing heterojunction bipolar transistors where the extrinsic parasitic base resistance and the extrinsic parasitic base-collector and base-emitter capacitances can be virtually eliminated and the base contact resistance can be greatly reduced. The method includes formming symmetric emitter and collector portions using front and backside processing of the wafer, respectively. The symmetric emitter and collector virtually eliminates the extrinsic collector and emitter regions of the device thereby virtually eliminating the extrinsic base-collector and base-emitter capacitance. The extrinsic base contact region may also be increased to minimize the base contact resistance without increasing parasitic capacitive elements of the device. Self-aligned processing features are also included to form self-aligned contacts to the base layer thereby virtually eliminating the extrinsic base resistance. The method may include building up the collector and emitter contacts to separate the emitter and collector interconnections from the base layer to avoid increasing the emitter-base and collector-base extrinsic parasitic capacitances and to minimize associated resistances and inductances. The method may further include forming etch stop layers to facilitate removing of the substrate to perform the backside processing and to accurately etch through the collector layer without etching the base layer.

Thermal contact conductance of metallic coated BiCaSrCuO superconductor/copper interfaces at cryogenic temperatures

Abstract: The effects of vapor deposited coatings on the thermal contact conductance of cold pressed, normal state BiCaSrCuO superconductor/oxygen-free copper interfaces were experimentally investigated over a pressure range of 200 to 2,000 kPa. Using traditional vapor deposition processes, thin coatings of indium or lead were applied to the superconductor material to determine the effect on the heat transfer occurring at the interface. The test data indicate that the contact conductance can be enhanced using these coatings, with indium providing the greater enhancement. The experimental program revealed the need for a better understanding and control of the vapor deposition process when using soft metallic coatings. Also, the temperature-dependent microhardness of copper was experimentally determined and found to increase by approximately 35 percent as the temperature decreased from 300 to 85 K. An empirical model was developed to predict the effect of soft coatings on the thermal contact conductance of the superconductor/copper interfaces. When applied, the model agreed well with the data obtained in this investigation at low coating thicknesses but overpredicted the data as the thickness increased. In addition, the model agreed very well with data obtained in a previous investigation for silvercoated nickel substrates at all coating thicknesses.

Effects of contact resistance on thermal conductivity of composite media with a periodic structure

Abstract: The thermal conductivity of periodic composite media with spherical or cylindrical inclusions embedded in a homogeneous matrix is discussed. Using Green functions, we show that the Rayleigh identity can be generalized to deal with thermal properties ot these systems. A new calculating method for effective conductivity of composite media is proposed. Useful formulae for effective thermal conductivity are derived, and meanings of contact resistance in engineering problems are explained.

A quarter-micron planarized interconnection technology with self-aligned plug

Abstract: In order to realize minimum pitch interconnections without degrading reliability, self-aligned contacts (SACs) between interconnections and plugs are necessary. The planarized interconnections with SAC plugs is formed for quarter-micron size as follows. Interconnection trenches and contact holes are formed using a self-aligned etch-stop layer, followed by simultaneous metal-filling into the trenches and contact holes. Si-rich oxide (SRO) films are found to be promising for a self-aligned etch-stop layer with their high etching selectivity to SiO/sub 2/ as high as 10-30. Sufficiently low line resistance of 15 k Omega /cm and low contact resistance of 70 Omega /contact are obtained with the quarter-micron W-interconnection with the SAC plugs. >

Test system with reduced test contact interface resistance

Abstract: An improved test system includes means for generating a contact wetting pulse and applying the contact wetting pulse to a network such that contact resistance at the interfaces between probes of the test system and terminals of the network is effectively lowered.

Sub-quarter-micrometer CMOS on ultrathin (400 AA) SOI

Abstract: MOS transistors with effective channel lengths down to 0.2 mu m have been fabricated in fully depleted, ultrathin (400 AA) silicon-on-insulator (SOI) films. These devices do not exhibit punchthrough, even for the smallest channel lengths, and have performance characteristics comparable to deep-submicrometer bulk transistors. The NMOS devices have a p/sup +/-polysilicon gate, and the PMOS devices have an n/sup +/-polysilicon gate, giving threshold voltages close to 1 V with very light channel doping. Because the series resistance associated with the source and drain regions can be very high in such thin SOI films, a titanium salicide process was used using a 0.25 mu m oxide spacer. With this process, the sheet resistance of the silicided SOI layer is approximately 5 Omega / Square Operator . However, the devices still exhibit significant series resistance, which is likely due to contact resistance between the silicide and silicon source/drain regions. >

Charge transfer between a polymer particle and a metal plate due to impact

Abstract: To elucidate the mechanism of contact-impact electrification of insulating particles, the authors measured the charge generated by collision of a single polymer particle onto a metal plate. It was not exclusively the normal component of the impact velocity that determined the amount of impact charging. In order to investigate this great contribution of the impact angle to the impact charging, impact stresses, contact times, and contact areas were measured, and the impact-contact process was discussed. Based on the idea that the "apparent contact area" is supported by some "real contact points" and that the number of these real contact points increases with the particle slipping, a new model called "effective contact area model" was proposed. >

Measuring molded case circuit breaker resistance

Abstract: Molded case circuit breaker resistance is measured under various conditions to demonstrate the need for more standardized procedures when performing millivolt drop measurements. Breakers, rated at 600 V/sub ac//250 A/sub ac/ and 120/240 V/sub ac//50 A/sub ac/, with silver-tungsten (Ag-W) contacts are used to show that contact resistance can cause variability in circuit breaker resistance and to demonstrate the influence of current, time, contact temperature, and applied voltage on contact resistance. Based on these results, guidelines are developed for making reliable resistance measurements on molded-case circuit breakers (MCCB) when using the millivolt drop technique. >

Ti/Pt/Au Ohmic Contacts to n-Type ZnSe

Abstract: We report that a Ti/Pt/Au multilayered metal structure can make a nonalloy ohmic contact to n-type ZnSe with an electron concentration greater than 1019 cm-3. A specific contact resistance as low as 3.4×10-4 Ω-cm2 was achieved for Cl-doped ZnSe with an electron concentration of 2×1019 cm-3. We think that the lower contact resistance can be ascribed to the higher reactivity and adhesion of Ti metal with the surface of ZnSe at low temperature, and to the lower work function of Ti metal. The dominant current flow may be due to the quantum mechanical tunneling of electrons through the potential barrier at the ZnSe surface, because the specific contact resistance decreases with an increase in the electron concentration. A small improvement in the specific contact resistance was made by thermal annealing at a temperature of 250°C for 5 min, which yielded the lowest value of 1.1×10-4 Ω-cm2. With annealing at 300°C and below, the contact resistance was not drastically increased. The electrical properties of the contact are therefore thermally stable up to 300°C.

Barrier metal contact architecture

Abstract: The interconnect system of the present invention is comprised of a TiW metal barrier layer as well as a Ti metal barrier layer deposited on the silicon surface. An anisotropic etch process for the Ti/TiW/Al metal sandwich has also been developed without corrosion and metal residue. The addition of the Ti layer between the TiW layer and the silicon surface reduces the contact resistance between the metal and P+ silicon contact. This Ti layer also effectively improves the blocking of aluminum migration to the silicon surface through TiW grain boundaries. In order to realize good ohmic metal-P+ contacts, the surface concentration of the silicon should be very high. Therefore, the present invention also employs a plasma mode etch which removes about 250 Å silicon since peak concentrations of P+ dopants (boron) are often found about 400 Å below the silicon surface. This plasma mode etch will also remove silicon damage caused by previous etching. A detailed etching process is also developed in the present invention so as to avoid any corrosion or metal residue.

Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance

Abstract: A process for manufacturing thin film transistors that have small source-drain areas, small gate-source parasitic capacitance C gs , and low contact resistance, comprising producing the gate of the transistor on a glass substrate, depositing a gate insulating layer, a thick undoped amorphous silicon layer and a top passivation layer successively on the substrate. The top passivation layer and the thick undoped amorphous silicon layer are then etched until the insulating layer is exposed.

Electrical characteristics of TiB/sub 2/ for ULSI applications

Abstract: The work function of TiB/sub 2/ was measured using Fowler-Nordheim tunneling in MOS capacitors, Schottky diode current measurements, capacitance-voltage techniques, and contact resistance. The resulting data place the Fermi level of TiB/sub 2/ about 0.9 eV below the silicon conduction band. Given this barrier height, Schottky diodes of TiB/sub 2//p-Si exhibit ohmic characteristics, but the contact resistance of TiB/sub 2/ to n/sup +/ junctions is an order of magnitude higher than the generally desired value. Boron outdiffusion from TiB/sub 2/ into underlying silicon was observed at temperatures of 1000 degrees C and greater. Boron diffusion from TiB/sub 2/ into silicon above 1000 degrees C is enhanced compared to the conventionally accepted value of the boron diffusivity. >

Wafer level reliability contact test structure and method

Abstract: A contact test structure and method provide accelerated testing of long term reliability of metal to silicon ohmic contacts and adjacent PN junctions on IC dies of a wafer. At least one wafer level reliability contact test structure (10) is formed on the wafer during CMOS or BICMOS wafer fabrication mask sequences without additional steps. A shallow layer (N+S/D) of semiconductor silicon material of second type carrier (N) conductivity is formed in a well (PWELL) of first type carrier (P) conductivity silicon material with a shallow PN junction (J) between the shallow layer and well. Metal to silicon first and second test contacts (TC1,TC2) of metal layer portions (M1) are formed at first and second locations on the shallow layer (N+S/D) spaced apart a selected distance. The second test contact (TC2) has a contact area between a metal layer (M1) and shallow layer (N+S/D) in the minimum size range for the fabrication process for maximizing current density through the second test contact (TC2). The first test contact (TC1) has a substantially greater contact area. A large current is forced in a conductive path through the shallow layer (N+S/D) between the first and second test contacts (TC1,TC2). Changes in the resistance of the conductive path caused by changes in the contact resistance of the second test contact TC2 over time are monitored as a function of applied first and second voltages (V1,V2) and forced current. Additional contact test structure is formed on the well with an ohmic contact layer (P+S/D) spaced from the shallow layer (N+S/D) and metal to silicon third test contact (TC3) to detect occurrence of junction spiking.

Modeling of the low-frequency base resistance of single base contact bipolar transistors

Abstract: The current and geometry dependence of the base resistance of single base contact (SBC) bipolar transistors is accurately modeled by extending the simple analytical formulas given by T. Ohzone et al. (1985). The results show that SBC transistors only seem to be useful if the ratio of emitter width b to emitter length l is larger than about 1/5. Of course, this limit depends on technology and circuit application. >

Moisture Effects Including Stiction Resulting From Adsorbed Water Films

Abstract: Stiction resulting from moisture effects at small elastic contact spots has been identified and studied using bundles of fine, gold-plated copper fibers sliding on a gold-plated copper surface. The relevant measurements were made in the hoop apparatus which permits simultaneous monitoring of the momentary coefficient of friction and electrical contact resistance. Previous studies made with the hoop apparatus have shown that under the action of high local pressure, adsorbed moisture is expelled from between the contact spots leaving only one monomolecular layer of adsorbed water on each of the contacting surfaces. Additional details of the observations are varied and permit a refined analysis. Stiction results during periods of very slow motion or rest through local energy reduction at the spots as excess water is slowly drained in the course of molecular ordering of the two absorbed layers. Complex variations of kinetic friction with humidity and sliding speed are explained through the interplay of excess molecules between the contact spot surfaces, meniscus formation, fluid drag about the spots, and shear thinning in that flow.

High Temperature Reliability of Refractory Metal Ohmic Contacts to Diamond

Abstract: : Several metallization schemes using refractory metals have been demonstrated to produce ohmic contacts to diamond via a solid-state reaction process. This process utilizes existing microelectronic techniques and provides strongly adherent contacts which exhibit low contact resistance. Measurements of the long-term reliability of Mo/Au contacts formed by this process on a type IIb diamond crystal are presented here for the temperature range 450 to 625 deg C. The measurements consist of the resistance between two contacts as a function of isothermal annealing time over time intervals in excess of 130 h in a purified inert ambient. The Mo/Au contacts appeared to be stable and reliable at these high temperatures with no indications of deterioration or degradation of performance.