Showing papers on "Contact resistance published in 2011"

The origins and limits of metal–graphene junction resistance

Abstract: A high-quality junction between graphene and metallic contacts is crucial in the creation of high-performance graphene transistors. In an ideal metal-graphene junction, the contact resistance is determined solely by the number of conduction modes in graphene. However, as yet, measurements of contact resistance have been inconsistent, and the factors that determine the contact resistance remain unclear. Here, we report that the contact resistance in a palladium-graphene junction exhibits an anomalous temperature dependence, dropping significantly as temperature decreases to a value of just 110 ± 20 Ω µm at 6 K, which is two to three times the minimum achievable resistance. Using a combination of experiment and theory we show that this behaviour results from carrier transport in graphene under the palladium contact. At low temperature, the carrier mean free path exceeds the palladium-graphene coupling length, leading to nearly ballistic transport with a transfer efficiency of ~75%. As the temperature increases, this carrier transport becomes less ballistic, resulting in a considerable reduction in efficiency.

Surface Doping of Conjugated Polymers by Graphene Oxide and Its Application for Organic Electronic Devices

Abstract: Conjugated polymers are a novel class of solution-processable semiconducting materials with intriguing optoelectronic properties. [ 1 ] They have received great attention as active components in organic electronic devices such as organic photovoltaic cells (OPVs), organic light-emitting diodes (OLEDs), and organic fi eld-effect transistors (OFETs) due to their light weight, facile tuning of electronic properties through molecular engineering, and ease of processing. The performance and lifetime of conjugated polymer-based electronic devices are critically dependent on the bulk properties of the active materials and the interfacial properties of electrode/polymer contacts. [ 2–4 ] In these devices, the electrode(s) either inject charge into or extract charges from the organic semiconductor layer(s). Mismatch of the work functions between metal or metal oxide electrodes and molecular orbital energy levels of organic semiconductors can lead to high contact resistance, which decreases the charge injection and extraction effi ciency. Therefore, it is essential to minimize contact resistance at the electrode/organic semiconductor interface. To improve charge injection/extraction across the electrode/ organic semiconductor interface, several strategies have been developed. One is to tune the interfacial dipole across the electrode/semiconductor interface to reduce the injection/collection energy barrier. This can be achieved by modifying the electrode surface with self-assembled dipolar molecules to tune the energy level alignment at the semiconductor/electrode interface. [ 5–7 ] Alternatively, the introduction of a thin layer of polymer surfactant that contains polar side chains between the conjugate polymer/electrode interface can also be used to improve the interfacial properties. The polar side chains can provide not

III-V layers for N-type and P-type MOS source-drain contacts

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.

Impact of Graphene Interface Quality on Contact Resistance and RF Device Performance

Abstract: This letter demonstrates the importance of the graphene/metal interface on the ohmic contacts of high-frequency graphene transistors grown by chemical vapor deposition (CVD) on copper. Using an Al sacrificial layer during ohmic lithography, the graphene surface roughness underneath the ohmic contacts is reduced by fourfold, resulting in an improvement in the contact resistance from 2.0 to 0.2-0.5 kΩ·μm. Using this technology, top-gated CVD graphene transistors achieved direct-current transconductances of 200 mS/mm, maximum on current densities in excess of 1000 mA/mm, and hole mobilities ~ 1500-3000 cm2/(V·s) on silicon substrates. Radio-frequency device performance yielded an extrinsic current-gain cutoff frequency fT of 12 GHz after pad capacitance de-embedding resulting in an fT - LG product of 24 GHz·μm.

Small hysteresis nanocarbon-based integrated circuits on flexible and transparent plastic substrate.

Abstract: We report small hysteresis integrated circuits by introducing monolayer graphene for the electrodes and a single-walled carbon nanotube network for the channel. Small hysteresis of the device originates from a defect-free graphene surface, where hysteresis was modulated by oxidation. This uniquely combined nanocarbon material device with transparent and flexible properties shows remarkable device performance; subthreshold voltage of 220 mV decade(-1), operation voltage of less than 5 V, on/off ratio of approximately 10(4), mobility of 81 cm(2) V(-1) s(-1), transparency of 83.8% including substrate, no significant transconductance changes in 1000 times of bending test, and only 36% resistance decrease at a tensile strain of 50%. Furthermore, because of the nearly Ohmic contact nature between the graphene and carbon nanotubes, this device demonstrated a contact resistance 100 times lower and a mobility 20 times higher, when compared to an Au electrode.

Carbon nanotube wires and cables: Near-term applications and future perspectives

Abstract: Wires and cables are essential to modern society, and opportunities exist to develop new materials with reduced resistance, mass, and/or susceptibility to fatigue. This article describes how carbon nanotubes (CNTs) offer opportunities for integration into wires and cables for both power and data transmission due to their unique physical and electronic properties. Macroscopic CNT wires and ribbons are presently shown as viable replacements for metallic conductors in lab-scale demonstrations of coaxial, USB, and Ethernet cables. In certain applications, such as the outer conductor of a coaxial cable, CNT materials may be positioned to displace metals to achieve substantial benefits (e.g.reduction in cable mass per unit length (mass/length) up to 50% in some cases). Bulk CNT materials possess several unique properties which may offer advantages over metallic conductors, such as flexure tolerance and environmental stability. Specifically, CNT wires were observed to withstand greater than 200,000 bending cycles without increasing resistivity. Additionally, CNT wires exhibit no increase in resistivity after 80 days in a corrosive environment (1 M HCl), and little change in resistivity with temperature (<1% from 170–330 K). This performance is superior to conventional metal wires and truly novel for a wiring material. However, for CNTs to serve as a full replacement for metals, the electrical conductivity of CNT materials must be improved. Recently, the conductivity of a CNT wire prepared through simultaneous densification and doping has exceeded 1.3 × 106 S/m. This level of conductivity brings CNTs closer to copper (5.8 × 107 S/m) and competitive with some metals (e.g.gold) on a mass-normalized basis. Developments in manipulation of CNT materials (e.g. type enrichment, doping, alignment, and densification) have shown progress towards this goal. In parallel with efforts to improve bulk conductivity, integration of CNT materials into cabling architectures will require development in electrical contacting. Several methods for contacting bulk CNT materials to metals are demonstrated, including mechanical crimping and ultrasonic bonding, along with a method for reducing contact resistance by tailoring the CNT-metal interface via electroless plating. Collectively, these results summarize recent progress in CNT wiring technologies and illustrate that nanoscale conductors may become a disruptive technology in cabling designs.

AlGaN/GaN High-Electron-Mobility Transistors Fabricated Through a Au-Free Technology

Abstract: This letter reports undoped AlGaN/GaN high-electron-mobility transistors (HEMTs) fabricated with a Si-CMOS-compatible technology based on Ti/Al/W ohmic and Schottky contacts. The use of ohmic recess is key to reduce the contact resistance of this Au-free metallization below 0.5 Ω·mm. Comparison of HEMTs fabricated on the same wafer with and without ohmic recess shows that the recess provides a tenfold reduction in contact resistance, resulting in a fivefold lower forward voltage drop at IDS = 100 mA/mm. The reported Au-free AlGaN/GaN HEMT fabrication technology provides similar performance (i.e., contact resistance, leakage current, and breakdown voltage) than state-of-the-art Au-based AlGaN/GaN HEMTs and can be used in standard Si fabs without the risk of contamination.

110 GHz measurement of large-area graphene integrated in low-loss microwave structures

Abstract: We report high-frequency scattering parameter measurement of large-area monolayer graphene integrated on low-loss quartz substrates. High-quality graphene was grown by chemical vapour deposition on copper, chemically hole doped, and transferred to quartz. Microwave measurements were performed from 0.01 to 110 GHz. Simple microwave models were used to extract graphene impedance parameters. We find that contact resistance is effectively shunted above 3 GHz. Atomically thin large area graphene behaves as a wideband resistor with negligible kinetic inductance and negligible skin effect.

Measuring the electrical resistivity and contact resistance of vertical carbon nanotube bundles for application as interconnects.

Abstract: Carbon nanotubes (CNT) are known to be materials with potential for manufacturing sub-20 nm high aspect ratio vertical interconnects in future microchips. In order to be successful with respect to contending against established tungsten or copper based interconnects, though, CNT must fulfil their promise of also providing low electrical resistance in integrated structures using scalable integration processes fully compatible with silicon technology. Hence, carefully engineered growth and integration solutions are required before we can fully exploit their potentialities. This work tackles the problem of optimizing a CNT integration process from the electrical perspective. The technique of measuring the CNT resistance as a function of the CNT length is here extended to CNT integrated in vertical contacts. This allows extracting the linear resistivity and the contact resistance of the CNT, two parameters to our knowledge never reported separately for vertical CNT contacts and which are of utmost importance, as they respectively measure the quality of the CNT and that of their metal contacts. The technique proposed allows electrically distinguishing the impact of each processing step individually on the CNT resistivity and the CNT contact resistance. Hence it constitutes a powerful technique for optimizing the process and developing CNT contacts of superior quality. This can be of relevant technological importance not only for interconnects but also for all those applications that rely on the electrical properties of CNT grown with a catalytic chemical vapor deposition method at low temperature.

Thermal conductivity and contact resistance of metal foams

Abstract: Accurate information on heat transfer and temperature distribution in metal foams is necessary for design and modelling of thermal-hydraulic systems incorporating metal foams. The analysis of heat transfer requires determination of the effective thermal conductivity as well as the thermal contact resistance (TCR) associated with the interface between the metal foam and the adjacent surfaces/layers. In this study, a test bed that allows the separation of effective thermal conductivity and TCR in metal foams is described. Measurements are performed in a vacuum under varying compressive loads using ERG Duocel aluminium foam samples with different porosities and pore densities. Also, a graphical method associated with a computer code is developed to demonstrate the distribution of contact spots and estimate the real contact area at the interface. Our results show that the porosity and the effective thermal conductivity remain unchanged with the variation of compression in the range 0‐2MPa; but TCR decreases significantly with pressure due to an increase in the real contact area at the interface. Moreover, the ratio of real to nominal contact area varies between 0 and 0.013, depending upon the compressive force, porosity, pore density and surface characteristics. (Some figures in this article are in colour only in the electronic version)

Electrical properties, microstructure, and thermal stability of Ta-based ohmic contacts annealed at low temperature for GaN HEMTs

Abstract: Ta-based ohmic contacts to gallium nitride high electron mobility transistor (GaN HEMT) epitaxial structures were investigated. Two metallization schemes were considered: Ta/Al/Ni(Ta)/Au and Ta/Al/Ta. The latter was superior in terms of lower contact resistance (R-c) and wider process window. The metallizations were applied to two different heterostructures (GaN/Al0.14Ga0.86N/GaN and Al0.25Ga0.75N/GaN). The lowest measured R-c was 0.06 and 0.28 Omega mm, respectively. The main advantage of the Ta-based ohmic contacts over conventional Ti-based contacts was the low anneal temperature. The optimum temperature of annealing was found to be 550-575 degrees C. From optical and scanning electron microscopy, it was clear that excellent surface morphology and edge acuity were obtained at these low temperatures. This facilitates lateral scaling of the GaN HEMT. TEM images were taken of the contact cross sections onto which EDX measurements were performed. The aim was to investigate the microstructure and the contact mechanism. Storage tests at 300 degrees C for more than 400 h in air ambient showed no deterioration of R-c.

Scanning thermal microscopy of individual silicon nanowires

Abstract: Thermal imaging of individual silicon nanowires (Si NWs) is carried out by a scanning thermal microscopy (SThM) technique. The vertically aligned 1.7 μm long Si NWs are fabricated combining nanosphere lithography and metal-induced wet chemical etching. A thermal model for the SThM probe is then presented with two steps: a model out of contact which enables a calibration of the probe, and a model in contact to extract thermal parameters from the sample under study. Using this model and the experimental thermal images, we finally determine a mean value of the tip-to-sample thermal contact resistance and a mean value of the Si NWs thermal conductivity. No significant thermal conductivity reduction in comparison with bulk Si is observed for Si NWs with diameters ranging from 200 to 380 nm. However, the technique presented here is currently the only one available to perform thermal measurements simultaneously on an assembly of individual one-dimensional nanostructures. It enables to save time and to make a sta...

Contact resistance in top-gated graphene field-effect transistors

Abstract: The parasitic resistance of different source/drain metals for top-gated graphene field-effect transistors was extracted by fitting the measured ID-VG data with a resistance model and was found to be a significant part of the total resistance of graphene field-effect transistors. The results show that Ti/Au gives relatively large contact resistance, about 7500 Ω·μm. Ni/Au contact shows better result compared to Ti/Au, which is around 2100 Ω·μm. The lowest contact resistance was given by Ti/Pd/Au, which is around 750 Ω·μm. The contact resistivity for Ti/Pd/Au source/drain contact is around 2 × 10−6 Ω·cm2, close to state of the art GaAs technology.

Density-of-States Limited Contact Resistance in Graphene Field-Effect Transistors

Abstract: Graphene has attracted much attention as one of promising candidates of future high-speed transistor materials because of its high carrier mobility of more than 10,000 cm2 V-1 s-1. Up to this point, we have focused on the contact properties as performance killers, as a very small density of states in graphene might suppress the current injection from metal to graphene. This paper systematically reviews the metal/graphene contact properties and discusses the present status and future requirements of the specific contact resistivity.

High performance indium-zinc-oxide thin-film transistors fabricated with a back-channel-etch-technique

Abstract: Indium-zinc-oxide thin-film transistors (TFTs) with back-channel-etch (BCE) structure were demonstrated. A stacked structure of Mo/Al/Mo was used as the source/drain electrodes and patterned by a wet-etch-method. Good etching profile with few residues on the channel was obtained. The TFT showed a field effect mobility of 11.3 cm2 V−1 s−1 and a sub-threshold swing of 0.24 V/decade. The performance of this kind of TFT was better than that of the TFT with etch-stopper-layer structure, which was proved to be due to the lower contact resistance. The BCE-TFTs fabricated with this method have good prospect due to the advantage of low cost.

Local Voltage Drop in a Single Functionalized Graphene Sheet Characterized by Kelvin Probe Force Microscopy

Abstract: We studied the local voltage drop in functionalized graphene sheets of subμm size under external bias conditions by Kelvin probe force microscopy. Using this noninvasive experimental approach, we measured ohmic current–voltage characteristics and an intrinsic conductivity of about 3.7 × 105 S/m corresponding to a sheet resistance of 2.7 kΩ/sq under ambient conditions for graphene produced via thermal reduction of graphite oxide. The contact resistivity between functionalized graphene and metal electrode was found to be <6.3 × 10–7 Ωcm2.

Contact resistance reduction employing germanium overlayer pre-contact metalization

Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.

Experimental evidence of direct contact formation for the current transport in silver thick film metallized silicon emitters

Abstract: Great advances have been achieved in the development of silver pastes. The use of smaller silver particles, higher silver content, and, thus, less glass frit allow modern silver pastes to contact high resistive emitters without the necessity of a selective emitter or subsequent plating. To identify the microscopic key reasons behind the improvement of silver paste, it is essential to understand the current transport mechanism from the silicon emitter into the bulk of the silver finger. Two current transport theories predominate: i) The current flows through the Ag crystallites grown into the Si emitter, which are separated by a thin glass layer or possibly in direct contact with the silver finger. ii) The current is transported by means of multistep tunneling into the silver finger across nano-Ag colloids in the glass layer, which are formed at optimal firing conditions; the formation of Ag crystallites into the Si surface is synonymous with over-firing. In this study, we contact Si solar cell emitters wi...

Silicon diffusion in aluminum for rear passivated solar cells

Abstract: We show that the lateral spread of silicon in a screen-printed aluminum layer increases by (1.50±0.06) μm/°C, when increasing the peak firing temperature within an industrially applicable range. In this way, the maximum spread limit of diffused silicon in aluminum is predictable and does not depend on the contact area size but on the firing temperature. Therefore, the geometry of the rear side pattern can influence not only series resistance losses within the solar cell but the process of contact formation itself. In addition, too fast cooling lead to Kirkendall void formations instead of an eutectic layer.

Simultaneous Modification of Bottom-Contact Electrode and Dielectric Surfaces for Organic Thin-Film Transistors Through Single-Component Spin-Cast Monolayers

Abstract: An efficient process is developed by spin-coating a single-component, self-assembled monolayer (SAM) to simultaneously modify the bottom-contact electrode and dielectric surfaces of organic thin-film transistors (OTFTs). This efficient interface modification is achieved using n-alkyl phosphonic acid based SAMs to prime silver bottom-contacts and hafnium oxide (HfO{sub 2}) dielectrics in low-voltage OTFTs. Surface characterization using near edge X-ray absorption fine structure (NEXAFS) spectroscopy, X-ray photoelectron spectroscopy (XPS), attenuated total reflectance Fourier transform infrared (ATR-FTIR) spectroscopy, atomic force microscopy (AFM), and spectroscopic ellipsometry suggest this process yields structurally well-defined phosphonate SAMs on both metal and oxide surfaces. Rational selection of the alkyl length of the SAM leads to greatly enhanced performance for both n-channel (C60) and p-channel (pentacene) based OTFTs. Specifically, SAMs of n-octylphos-phonic acid (OPA) provide both low-contact resistance at the bottom-contact electrodes and excellent interfacial properties for compact semiconductor grain growth with high carrier mobilities. OTFTs based on OPA modifi ed silver electrode/HfO{sub 2} dielectric bottom-contact structures can be operated using < 3V with low contact resistance (down to 700 Ohm-cm), low subthreshold swing (as low as 75 mV dec{sup -1}), high on/off current ratios of 107, and charge carrier mobilities as high as 4.6 and 0.8 cm{sup 2} V{supmore » -1} s{sup -1}, for C60 and pentacene, respectively. These results demonstrate that this is a simple and efficient process for improving the performance of bottom-contact OTFTs.« less

Impact of contact resistance on the transconductance and linearity of graphene transistors

Abstract: Interest in graphene device physics and technology has been growing rapidly, especially for very high frequency transistor applications. However, the predicted intrinsic performance has not been fully realized due to impurity and parasitic issues introduced in device fabrication. Through a self-consistent model, we show that the normalized contact resistance has an exponentially detrimental impact on the peak transconductance, which is a defining transistor parameter. In addition, we reveal that very high current-gate voltage linearity or input invariant transconductance can be achieved in the limit of negligible contact resistances, a desirable feature for linear electronic systems.

A study of the specific contact resistance and channel resistivity of amorphous IZO thin film transistors with IZO source–drain metallization

Abstract: We report on the specific contact resistance of interfaces between thin amorphous semiconducting IZO channel layers and IZO source/drain metallization in amorphous oxide thin film transistors (TFTs). As-deposited, low carrier density amorphous IZO layers are difficult to produce and consequently very thin (10–30 nm) channel layers are required for IZO TFT device applications in order to achieve adequately low off-state current. In this article, the transmission line model (TLM) and structures that also serve as IZO gate-down TFTs were used to examine IZO/IZO homojunctions with thin (10 nm) and thick (100 nm) channel layers. Thin, 10 nm, IZO channel devices with IZO source/drain contacts show a threshold voltage of −3.9 V and a very high specific contact resistance (ρC) that varies with gate voltage (VG) in the range 0–10 V from 460 to 130 Ω cm2. Annealing in air at 200 °C resulted in a tenfold improvement in ρC (34 Ω cm2) and corresponds to an increase in carrier density in the channel. Thicker IZO films...

Ohmic contact properties of magnetron sputtered Ti3SiC2 on n- and p-type 4H-silicon carbide

Abstract: Epitaxial Ti3SiC2 (0001) thin film contacts were grown on doped 4H-SiC (0001) using magnetron sputtering in an ultra high vacuum system. The specific contact resistance was investigated using linea ...

Self-aligned contact metallization for reduced contact resistance

Abstract: Techniques are disclosed for forming low contact resistance transistor devices. A p-type germanium layer is provided between p-type source/drain regions and their respective contact metals, and an n-type III-V semiconductor material layer is provided between n-type source/drain regions and their respective contact metals. The n-type III-V semiconductor material layer may have a small bandgap (e.g., <0.5 eV) and/or otherwise be doped to provide desired conductivity, and the p-type germanium layer can be doped, for example, with boron. After deposition of the III-V material over both the n-type source/drain regions and the germanium covered p-type source/drain regions, an etch-back process can be performed to take advantage of the height differential between n and p type regions to self-align contact types and expose the p-type germanium over p-type regions and thin the n-type III-V material over the n-type regions. The techniques can be used on planar and non-planar transistor architectures.

Structural and transport properties in alloyed Ti/Al Ohmic contacts formed on p-type Al-implanted 4H-SiC annealed at high temperature

Abstract: In this paper, the transport properties of alloyed Ti/Al Ohmic contacts formed on p-type Al-implanted silicon carbide (4H-SiC) were studied. The morphology of p-type implanted 4H-SiC was controlled using a capping layer during post-implantation activation annealing at 1700??C. The different morphological conditions do not affect the macroscopic electrical properties of the implanted SiC (such as the sheet resistance or the mobility). On the other hand, the improved morphology of implanted SiC allows us to achieve a flatter Ti/Al surface and a lower specific contact resistance. The temperature dependence of the specific resistance of the contacts was studied to obtain physical insights into the carrier transport mechanism at the metal/SiC interface. The fit comparing several models shows that thermionic field emission is the dominant transport mechanism through the metal/SiC interface, and that a reduction in the barrier height from 0.51 to 0.46?eV is associated with the improvement of the Ohmic properties. Transmission electron microscopy analysis showed the presence of a laterally inhomogeneous microstructure of the metal/SiC interface. The reduction in the barrier height could be correlated with the different microstructures of the interfacial region.

Substrate Gating of Contact Resistance in Graphene Transistors

Abstract: Metal contacts have been identified to be a key technological bottleneck for the realization of viable graphene electronics. Recently, it has been observed that for structures that possess both a top and a bottom gate, the electron-hole conductance asymmetry can be modulated by the bottom gate. In this paper, we explain this observation by postulating the presence of an effective thin interfacial dielectric layer between the metal contact and the underlying graphene. Electrical results from quantum transport calculations accounting for this modified electrostatics corroborate well with the experimentally measured contact resistances. This paper indicates that the engineering of a metal-graphene interface is a crucial step toward reducing the contact resistance for high-performance graphene transistors.