Contact resistance

About: Contact resistance is a research topic. Over the lifetime, 15262 publications have been published within this topic receiving 232144 citations. The topic is also known as: electrical contact resistance & ECR.

Multilayer probe for measuring electrical characteristics

Abstract: A probe structure containing a contact part (2) formed on one side (1a) of an insulating substrate (1), a conductive circuit (3) formed on the other side (1b) of the insulating substrate (1), wherein the contact part (2) and the conductive circuit (3) are connected via a conductive path (5) formed in a through-hole (4) in the thickness direction of the insulating substrate (1). The contact part (2) has a structure containing a deep layer (1c) having a hardness of 100-700 Hk, an intermediate layer (1b) having a hardness of 10-300 Hk, and a surface layer (1a) having a hardness of 700-1200 Hk successively laminated. The surface layer (1a) preferably has a tensile stress of not more than 50 kg/mm 2 . The probe structure maintains low and stable contact resistance in an electric test, in particular a burn-in test, of small test objects such as IC. In a test method wherein a solder bump is formed in a test object and utilized, the solder component of the test object does not adhere to the contact part (2) after testing. The probe structure suffers less from deterioration of contact state after repetitive open/close contact with the test object as compared to the initial contact state, and highly reliable electric testing can be performed.

Low contact resistance and low junction leakage metal interconnect contact structure

Abstract: A low contact resistance and low junction leakage metal interconnect contact structure for use with ICs. The contact structure includes an interconnect dielectric material layer on the surface of an IC semiconductor substrate. The interconnect dielectric material layer has a contact opening which extends to a predetermined region of the semiconductor substrate (e.g. a source region, drain region, or polysilicon gate layer). The contact structure also includes a cobalt (or nickel) silicide interface layer on the surface of the predetermined region that is aligned with the bottom of the contact opening, a cobalt (or nickel) adhesion layer on the sidewall surface of the contact opening, a refractory metal-based barrier layer on the metal adhesion layer and the metal silicide interface layer, and a conductive plug. Manufacturing process steps for such a contact structure include first providing a semiconductor substrate with at least one predetermined region (e.g. a drain region, source region or polysilicon gate layer), followed by depositing an interconnect dielectric material layer on the surface of the semiconductor substrate. Contact openings are formed through the interconnect dielectric material layer to expose the predetermined region. A cobalt (or nickel) adhesion layer is then deposited, followed by the deposition of a refractory metal-based barrier layer, and the reaction of cobalt (or nickel) from the adhesion layer with silicon from the exposed predetermined region to form a metal silicide interface layer. Finally, a conductive plug layer is deposited on the barrier layer, filling the contact opening.

Selective and localized laser annealing effect for high-performance flexible multilayer MoS2 thin-film transistors

Abstract: We report the use of ultra-short, pulsed-laser annealed Ti/Au contacts to enhance the performance of multilayer MoS2 field effect transistors (FETs) on flexible plastic substrates without thermal damage. An analysis of the temperature distribution, based on finite difference methods, enabled understanding of the compatibility of our picosecond laser annealing for flexible poly(ethylene naphthalate) (PEN) substrates with low thermal budget (< 200 °C). The reduced contact resistance after laser annealing provided a significant improvement in transistor performance including higher peak field-effect mobility (from 24.84 to 44.84 cm2·V−1·s−1), increased output resistance (0.42 MΩ at V gs − V th = 20 V, a three-fold increase), a six-fold increase in the self-gain, and decreased sub-threshold swing. Transmission electron microscopy analysis and current-voltage measurements suggested that the reduced contact resistance resulted from the decrease of Schottky barrier width at the MoS2-metal junction. These results demonstrate that selective contact laser annealing is an attractive technology for fabricating low-resistivity metal-semiconductor junctions, providing important implications for the application of high-performance two-dimensional semiconductor FETs in flexible electronics.