Contact resistance

About: Contact resistance is a research topic. Over the lifetime, 15262 publications have been published within this topic receiving 232144 citations. The topic is also known as: electrical contact resistance & ECR.

Silicide contacts having different shapes on regions of a semiconductor device

Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

Contact resistance in organic thin film transistors

Abstract: This letter reports on the unexpected dependence of contact resistance on the dielectric layer for pentacene thin film transistors with printed organic conducting electrodes. While the intrinsic mobility is weakly reliant on the dielectric, the contact resistance does vary considerably with dielectric layer. We show that while morphological changes are not apparent, contact resistances vary by an order of magnitude. This result suggests that the barrier to charge injection may depend not only on interactions at the complex triple interface but also on the details of the electronic structure at the semiconductor/dielectric interface.

Transferred via contacts as a platform for ideal two-dimensional transistors

Abstract: Two-dimensional semiconductors have a number of valuable properties that could be used to create novel electronic devices. However, creating 2D devices with good contacts and stable performance has proved challenging. Here we show that transferred via contacts, made from metal embedded in insulating hexagonal boron nitride and dry transferred onto 2D semiconductors, can be used to create high-quality 2D transistors. The approach prevents damage induced by direct metallization and allows full glovebox processing, providing a clean, stable and damage-free platform for 2D device fabrication. Using the approach, we create field-effect transistors (FETs) from bilayer p-type tungsten diselenide (WSe2) that exhibit high hole mobility and low contact resistance. The fabricated devices also exhibit high current and stability for over two months of measurements. Furthermore, the low contact resistance and clean channel allow us to create a nearly ideal top-gated p-FET with a subthreshold swing of 64 mV per decade at 290 K. Bilayer WSe2 field-effect transistors with near ideal device characteristics can be created using transferred via contacts made from metal-embedded hexagonal boron nitride.

Ultra-low resistance ohmic contacts in graphene field effect transistors

Abstract: We report on an experimental demonstration of graphene-metal ohmic contacts with contact resistance below 100 Ω µm. These have been fabricated on graphene wafers, both with and without hydrogen intercalation, and measured using the transmission line method. Specific contact resistivities of 3 × 10−7 to 1.2 × 10−8 Ω cm2 have been obtained. The ultra-low contact resistance yielded short-channel (source-drain distance of 0.45 µm) HfO2/graphene field effect transistors (FETs) with a low on-resistance (Ron) of 550 Ω µm and a high current density of 1.7 A/mm at a source-drain voltage of 1 V. These values represent state-of-the-art (SOA) performance in graphene-metal contacts and graphene FETs. This ohmic contact resistance is comparable to that of SOA high-speed III–V high electron mobility transistors.

Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same

Abstract: A method for fabricating an insulating layer having contact openings of varying depths for logic/DRAM circuits is achieved using a single mask and etch step. After forming stacked or trench capacitors, a planar insulating layer is formed. Contact openings are etched in the planar insulating layer to the substrate, and contact openings that extend over the edge of the stacked or trench capacitor top electrode, having an ARC, are etched using a novel mask design and a single etching step. This allows one to make contacts to the substrate without overetching while making low-resistance contacts to the sidewall of the capacitor top electrode. In the trench capacitor open areas are formed to facilitate making contact openings that extend over the top electrode. A series of contact openings that are skewed or elongated also improve the latitude in alignment tolerance.