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Contact resistance

About: Contact resistance is a research topic. Over the lifetime, 15262 publications have been published within this topic receiving 232144 citations. The topic is also known as: electrical contact resistance & ECR.


Papers
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Journal ArticleDOI
TL;DR: In this paper, the authors used a thin layer of polymer electrolyte (PE) consisting of poly(ethylene oxide) (PEO) and lithium perchlorate (LiClO4) as both a contact-barrier reducer and channel mobility booster.
Abstract: We report electrical characterization of monolayer molybdenum disulfide (MoS2) devices using a thin layer of polymer electrolyte (PE) consisting of poly(ethylene oxide) (PEO) and lithium perchlorate (LiClO4) as both a contact-barrier reducer and channel mobility booster. We find that bare MoS2 devices (without PE) fabricated on Si/SiO2 have low channel mobility and large contact resistance, both of which severely limit the field-effect mobility of the devices. A thin layer of PEO/LiClO4 deposited on top of the devices not only substantially reduces the contact resistance but also boost the channel mobility, leading up to three-orders-of-magnitude enhancement of the field-effect mobility of the device. When the PE is used as a gate medium, the MoS2 field-effect transistors exhibit excellent device characteristics such as a near ideal subthreshold swing and an on/off ratio of 106 as a result of the strong gate-channel coupling.

136 citations

Journal ArticleDOI
TL;DR: In this paper, the authors used the transfer line method to estimate the gate-voltage dependent mobility of OFTs with bottom-gate, top-contact architecture on alumina substrates.

136 citations

Journal ArticleDOI
TL;DR: In this paper, the authors reported reduced contact resistance of single-layer graphene devices by using ultraviolet ozone (UVO) treatment to modify the metal/graphene contact interface.
Abstract: We report reduced contact resistance of single-layer graphene devices by using ultraviolet ozone (UVO) treatment to modify the metal/graphene contact interface. The devices were fabricated from mechanically transferred, chemical vapor deposition (CVD) grown, single layer graphene. UVO treatment of graphene in the contact regions as defined by photolithography and prior to metal deposition was found to reduce interface contamination originating from incomplete removal of poly(methyl methacrylate) (PMMA) and photoresist. Our control experiment shows that exposure times up to 10 minutes did not introduce significant disorder in the graphene as characterized by Raman spectroscopy. By using the described approach, contact resistance of less than 200 {\Omega} {\mu}m was achieved, while not significantly altering the electrical properties of the graphene channel region of devices.

135 citations

Journal ArticleDOI
TL;DR: In this paper, the influence of Ti top electrode material on the resistive switching properties of ZrO2-based memory film using Pt as bottom electrode was investigated and the experimental results imply that switching the device into high conducting state is a field driven process while switching back into low conducting state was a current driven process.
Abstract: The influence of Ti top electrode material on the resistive switching properties of ZrO2-based memory film using Pt as bottom electrode was investigated in the present study. When Ti is used as top electrode, the resistive switching behavior becomes dependent on bias polarity and no current compliance is needed during switching into high conducting state. This phenomenon is attributed to the fact that a series resistance between Ti and ZrO2 film, composed of a TiOx layer, a ZrOy layer, and even the contact resistance, imposed a current compliance on the memory device. Besides, our experimental results imply that switching the device into high conducting state is a field driven process while switching back into low conducting state is a current driven process.

135 citations

Patent
Jin-Aun Ng1, Yu-Ying Hsu1, Chi-Ju Lee1, Sin-Hua Wu1, Bao-Ru Young1, Harry-Hak-Lay Chuang1 
24 Mar 2010
TL;DR: In this paper, the authors describe a trimming back nitride spacers for replacement gates, which allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process.
Abstract: The embodiments of methods described in this disclosure for trimming back nitride spacers for replacement gates allows the hard mask layers (or hard mask) to protect the polysilicon above the high-K dielectric during trim back process. The process sequence also allows determining the trim-back amount based on the process uniformity (or control) of nitride deposition and nitride etchback (or trimming) processes. Nitride spacer trim-back process integration is critical to avoid creating undesirable consequences, such as silicided polyisicon on top of high-K dielectric described above. The integrated process also allows widening the space between the gate structures to allow formation of silicide with good quality and allow contact plugs to have sufficient contact with the silicide regions. The silicide with good quality and good contact between the contact plugs and the silicide regions increase the yield of contact and allows the contact resistance to be in acceptable and workable ranges.

134 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023213
2022432
2021286
2020384
2019528
2018503