scispace - formally typeset
Search or ask a question
Topic

Contact resistance

About: Contact resistance is a research topic. Over the lifetime, 15262 publications have been published within this topic receiving 232144 citations. The topic is also known as: electrical contact resistance & ECR.


Papers
More filters
Journal ArticleDOI
TL;DR: For the first time, it is demonstrated that the 2DSC transistors can offer comparable performance to the 2017 target for silicon transistors in International Technology Roadmap for Semiconductors (ITRS), marking an important milestone in 2 DSC electronics.
Abstract: Two-dimensional semiconductors (2DSCs) such as molybdenum disulfide (MoS2) have attracted intense interest as an alternative electronic material in the postsilicon era. However, the ON-current density achieved in 2DSC transistors to date is considerably lower than that of silicon devices, and it remains an open question whether 2DSC transistors can offer competitive performance. A high current device requires simultaneous minimization of the contact resistance and channel length, which is a nontrivial challenge for atomically thin 2DSCs, since the typical low contact resistance approaches for 2DSCs either degrade the electronic properties of the channel or are incompatible with the fabrication process for short channel devices. Here, we report a new approach toward high-performance MoS2 transistors by using a physically assembled nanowire as a lift-off mask to create ultrashort channel devices with pristine MoS2 channel and self-aligned low resistance metal/graphene hybrid contact. With the optimized cont...

110 citations

Journal ArticleDOI
TL;DR: A simple and rapid pre-treatment washing method was proposed to reduce the thickness of PVP layer from 13.19 to 0.96 nm and improve the contact between wires, and the improved AgNWs were successfully employed in a capacitive pressure sensor with high transparency, sensitivity, and reproducibility.
Abstract: Transparent electrode based on silver nanowires (AgNWs) emerges as an outstanding alternative of indium tin oxide film especially for flexible electronics. However, the conductivity of AgNWs transparent electrode is still dramatically limited by the contact resistance between nanowires at high transmittance. Polyvinylpyrrolidone (PVP) layer adsorbed on the nanowire surface acts as an electrically insulating barrier at wire–wire junctions, and some devastating post-treatment methods are proposed to reduce or eliminate PVP layer, which usually limit the application of the substrates susceptible to heat or pressure and burden the fabrication with high-cost, time-consuming, or inefficient processes. In this work, a simple and rapid pre-treatment washing method was proposed to reduce the thickness of PVP layer from 13.19 to 0.96 nm and improve the contact between wires. AgNW electrodes with sheet resistances of 15.6 and 204 Ω sq−1 have been achieved at transmittances of 90 and 97.5 %, respectively. This method avoided any post-treatments and popularized the application of high-performance AgNW transparent electrode on more substrates. The improved AgNWs were successfully employed in a capacitive pressure sensor with high transparency, sensitivity, and reproducibility.

110 citations

Patent
05 Mar 1997
TL;DR: In this paper, a P-type electrode is used to keep high in crystallinity, low a contact resistance, and high enough in adhesive strength to an InAlGaN layer by a method wherein a first metal layer which contains an element component selected out of either group IV elements or group VI elements is deposited on a contact region.
Abstract: PROBLEM TO BE SOLVED: To realize a semiconductor light emitting device which is equipped with a P-type electrode which is kept high in crystallinity, low a contact resistance, and high enough in adhesive strength to an InAlGaN layer by a method wherein a first metal layer which contains an element component selected out of either group IV elements or group VI elements is deposited on a contact region. SOLUTION: A light emitting device 10 is possessed of a semiconductor multilayered structure deposited on a sapphire substrate 12. A buffer layer 14, an N-type contact layer 16, an N-type clad layer 18, an active layer 20, a P-type clad layer 22, and a P-type contact layer 24 are laminated in this sequence on the sapphire substrate 12. A P-type electrode layer 26 is deposited on the P-type contact layer 24. An N-type electrode layer 34 is deposited o the N-type contact layer 16. When an alloy of gold or the like and a group IV element or a group VI element is deposited, it is excellent in crystallinity. That is, the P-type electrode 26 is kept high in adhesive strength to the N-type contact layer 24 and can be lessened in contact resistance.

110 citations

Journal ArticleDOI
TL;DR: In this article, the transport characteristics of 70nm-diameter platinum nanowires (NWs), fabricated using a pore-templated electrodeposition process and individually contacted using a focused ion beam (FIB) method, are reported.
Abstract: The transport characteristics of 70-nm-diameter platinum nanowires (NWs), fabricated using a pore-templated electrodeposition process and individually contacted using a focused ion beam (FIB) method, are reported. This approach yields nanowire devices with low contact resistances (∼400Ω) and linear current–voltage characteristics for current densities up to 65kA∕cm2. The intrinsic nanowire resistivity (33±5μΩcm) indicates significant contributions from surface- and grain-boundary scattering mechanisms. Fits to the temperature dependence of the intrinsic NW resistance confirm that grain-boundary scattering dominates surface scattering (by more than a factor of 2) at all temperatures. Our results demonstrate that FIB presents a rapid and flexible method for the formation of low-resistance ohmic contacts to individual metal nanowires, allowing intrinsic nanowire transport properties to be probed.

109 citations

Journal ArticleDOI
TL;DR: The new nanostructured 3D current collector is demonstrated with a polyaniline (PANI)-based electrode system and is shown to deliver improved rate capability characteristics compared to planar configurations.
Abstract: Conventional thin film batteries are fabricated based on planar current collector designs where the high contact resistance between the current collector and electrodes impedes overall battery performance. Hence, current collectors based on 3D architectures and nanoscale roughness has been proposed to dramatically increase the electrode-current collector surface contact areas and hence significantly reduce interfacial resistance. The nanorod-based current collector configuration is one of several 3D designs which has shown high potential for the development of high energy and high power microbatteries in this regard. Herein we fabricate a nanoporous nanorod based current collector, which provides increased surface area for electrode deposition arising from the porosity of each nanorods, yet keeping an ordered spacing between nanorods for the deposition of subsequent electrolyte and electrode layers. The new nanostructured 3D current collector is demonstrated with a polyaniline (PANI)-based electrode system and is shown to deliver improved rate capability characteristics compared to planar configurations. We have been able to achieve stable capacities of ~32 μAh/cm(2) up to 75 cycles of charge/discharge even at a current rate of ~0.04 mA/cm(2) and have observed good rate capability even at high current rates of ~0.8 mA/cm(2).

109 citations


Network Information
Related Topics (5)
Silicon
196K papers, 3M citations
89% related
Thin film
275.5K papers, 4.5M citations
88% related
Dielectric
169.7K papers, 2.7M citations
85% related
Band gap
86.8K papers, 2.2M citations
85% related
Oxide
213.4K papers, 3.6M citations
83% related
Performance
Metrics
No. of papers in the topic in previous years
YearPapers
2023213
2022432
2021286
2020384
2019528
2018503