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Control logic

About: Control logic is a research topic. Over the lifetime, 4718 publications have been published within this topic receiving 42613 citations.


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Patent
03 Jan 2013
TL;DR: In this paper, the authors present a system and method in a building or vehicle for an actuator operation in response to a sensor according to a control logic, the system comprising a router or a gateway communicating with a device associated with the sensor, and an external Internet-connected control server associated with control logic implementing a PID closed linear control loop and communicating with the router over external network for controlling the in-building or in-vehicle phenomenon.
Abstract: A system and method in a building or vehicle for an actuator operation in response to a sensor according to a control logic, the system comprising a router or a gateway communicating with a device associated with the sensor and a device associated with the actuator over in-building or in-vehicle networks, and an external Internet-connected control server associated with the control logic implementing a PID closed linear control loop and communicating with the router over external network for controlling the in-building or in-vehicle phenomenon. The sensor may be a microphone or a camera, and the system may include voice or image processing as part of the control logic. A redundancy is used by using multiple sensors or actuators, or by using multiple data paths over the building or vehicle internal or external communication. The networks may be wired or wireless, and may be BAN, PAN, LAN, WAN, or home networks.

590 citations

Book ChapterDOI
21 Jun 1994
TL;DR: The method handles more complicated designs, and requires less human intervention, than existing methods, and results from an efficient validity checker for a logic of uninterpreted functions with equality.
Abstract: We describe a technique for verifying the control logic of pipelined microprocessors. It handles more complicated designs, and requires less human intervention, than existing methods. The technique automatically compares a pipelined implementation to an architectural description. The CPU time needed for verification is independent of the data path width, the register file size, and the number of ALU operations. Debugging information is automatically produced for incorrect processor designs. Much of the power of the method results from an efficient validity checker for a logic of uninterpreted functions with equality. Empirical results include the verification of a pipelined implementation of a subset of the DLX architecture.

589 citations

Journal ArticleDOI
TL;DR: In this paper, a real-time adaptive signal phase allocation algorithm using connected vehicle data is proposed to optimize the phase sequence and duration by solving a two-level optimization problem, which minimizes the total vehicle delay and minimizes queue length.
Abstract: The state of the practice traffic signal control strategies mainly rely on infrastructure based vehicle detector data as the input for the control logic. The infrastructure based detectors are generally point detectors which cannot directly provide measurement of vehicle location and speed. With the advances in wireless communication technology, vehicles are able to communicate with each other and with the infrastructure in the emerging connected vehicle system. Data collected from connected vehicles provides a much more complete picture of the traffic states near an intersection and can be utilized for signal control. This paper presents a real-time adaptive signal phase allocation algorithm using connected vehicle data. The proposed algorithm optimizes the phase sequence and duration by solving a two-level optimization problem. Two objective functions are considered: minimization of total vehicle delay and minimization of queue length. Due to the low penetration rate of the connected vehicles, an algorithm that estimates the states of unequipped vehicle based on connected vehicle data is developed to construct a complete arrival table for the phase allocation algorithm. A real-world intersection is modeled in VISSIM to validate the algorithms. Results with a variety of connected vehicle market penetration rates and demand levels are compared to well-tuned fully actuated control. In general, the proposed control algorithm outperforms actuated control by reducing total delay by as much as 16.33% in a high penetration rate case and similar delay in a low penetration rate case. Different objective functions result in different behaviors of signal timing. The minimization of total vehicle delay usually generates lower total vehicle delay, while minimization of queue length serves all phases in a more balanced way.

395 citations

Patent
08 Aug 2007
TL;DR: In this paper, a control circuit to control a speed of a motor includes a control logic circuit connected to a multifunction port, which is configured to receive a control signal provided at the multifunction and to provide response signals based on the control signal to place the motor in at least two of a sleep mode, a brake mode and a pulsewidth modulation (PWM) mode.
Abstract: In one aspect, a control circuit to control a speed of a motor includes a control logic circuit connected to a multifunction port. The control logic circuit is configured to receive a control signal provided at the multifunction port and to provide response signals based on the control signal to place the motor in at least two of a sleep mode, a brake mode and a pulse-width modulation (PWM) mode. The motor control circuit also includes an H-bridge circuit configured to control the motor based on the response signals.

372 citations

Journal ArticleDOI
TL;DR: The proposed algorithm for optimal state assignment is based on an innovative strategy: logic minimization of the combinational component of the finite state machine is applied before state encoding, and has been coded in a computer program, KISS, and tested on several examples of finite state machines.
Abstract: Computer-Aided synthesis of sequential functions of VLSI systems, such as microprocessor control units, must include design optimization procedures to yield area-effective circuits. We model sequential functions as deterministic synchronous Finite State Machines (FSM's), and we consider a regular and structured implementation by means of Programmable Logic Arrays (PLA's) and feedback registers. State assignment, i.e., binary encoding of the internal states of the finite state machine, affects substantially the silicon area taken by such an implementation. Several state assignment techniques have been proposed in the past. However, to the best of our knowledge, no Computer-Aided Design tool is in use today for an efficient encoding of control logic. We propose an algorithm for optimal state assignment. Optimal state assignment is based on an innovative strategy: logic minimization of the combinational component of the finite state machine is applied before state encoding. Logic minimization is performed on a symbolic (code independent) description of the finite state machine. The minimal symbolic representation defines the constraints of a new encoding problem, whose solutions are the state assignments that allow the implementation of the PLA with at most as many product-terms as the cardinality of the minimal symbolic representation. In this class, an optimal encoding is one of minimal length satisfying these constraints. A heuristic algorithm constructs a solution to the constrained encoding problem. The algorithm has been coded in a computer program, KISS, and tested on several examples of finite state machines. Experimental results have shown that the method is an effective tool for designing finite state machines.

340 citations


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Performance
Metrics
No. of papers in the topic in previous years
YearPapers
202314
202239
202186
2020230
2019260
2018244