Showing papers on "Control reconfiguration published in 1979"

Advanced mobile phone service: Cell-site hardware

Abstract: The hardware facilities of the amps cell site connect the mobile radio customer to the land telephone network and perform actions necessary for rf radiation, reception, and distribution; voice and data communications and processing; equipment testing, control, and reconfiguration; and call setup, supervision, and termination. Cell-site operational control is achieved partially through wired logic and partially through programmable controllers. This paper describes the cell-site functional groups, their physical characteristics and design, and the ways they interface with the rest of the amps system.

Local Reconfiguration of Networks of Processors.

Abstract: : This paper studies a local approach to reconfiguration of networks of processors, in which new connections are created only between pairs of processors that have a common neighbor Algorithms for transforming strings into cycles, trees, arrays, hypercubes, cliques, stars and wheels, and vice versa are presented The generation of all possible configurations of a given set of processors is also discussed (Author)

Local Reconfiguration of Networks of Processors: Arrays, Trees, and Graphs.

Abstract: : This paper studies local reconfiguration of trees into arrays and vice versa. It also studies the construction of adjacency graphs and quadtrees for images stored in cellular array processors. (Author)

Design Of A Fault-Tolerant Microprocessor

Abstract: Following an overview of the general practice in the reliable design of digital systems and the discussion of those design considerations for selfchecking and fault tolerant machines, the Self- Checking Microprocessor proposed by Maki (3) is brought to the readers' attention. Then the posibility of using this self-checking design in a hybrid-redundant microprocessor system is explored. In this paper, the self-checking processor and the main memory unit are triplicated for the purposeof error detection and momentary fault masking. Reconfiguration, allowing stand by units to replace failed unit, is possible due to the intelligence of the individual processors. Similarly the memory modules can be switched ON/OFF line by an additional self-checking processor incorporated into the design assuming the task of the majority voter of this TMR system.

Diagnosis of Faults in Modular Trees

Abstract: Diagnosis of stuck-at faults (s-a-f's) in modular trees is studied. Detection conditions for each distinguishable s-a-f in a module are derived. For single s-a-f's, the detection conditions are easily partitioned to achieve fault location by performing a small number of additional tests. A multiple s-a-f that produces the same test result as a single s-a-f can be located by applying additional tests whose number grows with the tree depth. All other multiple s-a-f's are detected but cannot be located. In this paper location algorithms for combinational modular trees are presented in detail. They are then modified to locate faults in modular trees which realize arbitrary definite machines. Since a pair of these tree structures can be connected to realize arbitrary sequential machines, the results derived here are useful in diagnosing sequential machines. The ability to diagnose faults, combined with the fact that the function of the tree is easily altered, makes this structure attractive in reconfiguration applications. In particular, application to array processors is suggested.

Data processing system re-configuration module - has first processor for managing re-configuration requests associated with control circuitry

Abstract: The reconfiguration module has first processing circuits for the management of reconfiguration requests which is associated with control circuits of various reconfigurable units. The control circuits include a first reconfigurable data memorising register, the data emanating from various central processors. A second register receives multiplexed data from either the first register or a control desk for determination of the reconfigurable units. The contents of the second register are displayed on the control desk. The desk has control circuits associated with each reconfigurable unit. It has also a circuit which assignas a reconfigurable unit and a second circuit which indicates its nonavailability.

Parallel fault-tolerant computation structure

Abstract: A parallel fault-tolerant computation structure (p.f.t.n.) is introduced, consisting of a control structure and a device structure. The control structure (c.f.n.) models parallel-system synchronisation and graceful degradation by reconfiguration after fault occurrence. The device structure models the parallel data flow. Liveness conditions of a c.f.n. are discussed, and a relationship between liveness and net configuration is developed and proved.

An application of simulation to tracking

Abstract: The AIMER project (Automatic Integration of Multiple Element Radars) is an emulated model of a loosely coupled distributed radar tracking processor. The computational elements of the model are minicomputers similar to the PDP-11. Design goals of the model are to provide a reliable processing system whose computational bandwidth can be dynamically altered in response to changing ground scenario and availability of hardware. A large number of minicomputers connected with multiple packet networks was chosen as the framework for the design.Building such a network with real computers would not have provided the required reconfiguration flexibility, and so a hybrid simulation/emulation approach was chosen. The instruction set of the minicomputer family is emulated, which allows performance monitoring to be an integral part of the system. Simulation is the key to controlled experiments and comprehensive throughput analysis. The radar and ground environments are simulated with logic residing in one of the emulated minicomputers. The use of this simulation technique has resulted in an extremely flexible test bed for the development of distributed radar tracking system models. The test bed itself can be quickly tailored to other application problems.This model is implemented on a Nanodata QM-1 emulation support computer. The QM-1 has two levels of microprogram control store, which allow implementor man hours and efficiency to be traded off conveniently.

Emergency State Control For Power Station Operating Using Process Computer

Abstract: Emergency state control is an important research topic which presently receives a lot of attention [1]. For this operating condition the design of a digital power station control is discussed in this paper for a specific model using pseudo-frequency domain analysis in this manner it is possible to derive DDC units for each control loop such that prespecified step responses of the process variables are obtained. Furthermore it is possible to guarantee that the admissible rates of change are fully exploited without exceeding them. Using interactive computing methods in the pseudo-frequency domain results in digital control structures which widely differ from the present ones. Since the numerical implementation is straight forward it seems realistic that the improved power reserve and stability behaviour may substantially contribute towards emergency state control.

Zugriffsfunktionen zur Unterstützung der Speicherverwaltung beim virtuellen Maschinenbetrieb

Abstract: When designing virtual machine systems memory management becomes a problem because the virtual machines must be kept from handling physical addresses. A method is proposed that neither needs much hardware nor does it produce software overhead. This method consists in a set of access functions that are implemented as privileged machine instructions. These instructions are described and their usage is demonstrated using a characteristic example. The implications of the access functions on real machine operation and reconfiguration are outlined and the possible limitations of this approach are discussed.